| 制造商 | 部件名 | 数据表 | 功能描述 |
 Texas Instruments |
CD54HC10
|
265Kb/10P
|
High-Speed CMOS Logic Triple 3-Input NAND Gate
|
|
CD54HC10
|
261Kb/11P
|
High-Speed CMOS Logic Triple 3-Input NAND Gate
|
|
CD54HC10
|
32Kb/5P
|
High-Speed CMOS Logic Triple 3-Input NAND Gate
|
|
CD54HC10
|
614Kb/15P
|
High-Speed CMOS Logic Triple 3-Input NAND Gate
|
|
CD54HC10
|
1Mb/26P
|
CDx4HC10 Triple 3-Input NAND Gates
REVISED JULY 2021
|
|
CD54HC107
|
266Kb/11P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC107
|
451Kb/15P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC107
|
624Kb/16P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC107
|
609Kb/20P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
Revised October 2003
|
|
CD54HC107F3A
|
266Kb/11P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC107F3A
|
451Kb/15P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC107F3A
|
624Kb/16P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC107F3A
|
609Kb/20P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
Revised October 2003
|
|
CD54HC107F3A.A
|
609Kb/20P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
Revised October 2003
|
|
CD54HC107
|
451Kb/15P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC107
|
624Kb/16P
|
Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
|
CD54HC109
|
279Kb/12P
|
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
|
|
CD54HC109
|
347Kb/16P
|
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
|
|
CD54HC109
|
454Kb/15P
|
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
|
|
CD54HC109
|
367Kb/16P
|
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
Revised October 2003
|