DESCRIPTION
Silicon N-channel enhancement mode vertical D-MOS transistor encapsulated in a 4-lead, SOT121 flange package, with a ceramic cap. All leads are isolated from the flange. A marking code, showing gate-source voltage (VGS) information is provided for matched pair applications. Refer to the General section of Data Handbook SC19a for further information.

FEATURES
• High power gain
• Low noise figure
• Easy power control
• Good thermal stability
• Withstands full load mismatch.

APPLICATIONS
• Large signal amplifier applications in the VHF frequency
   range.