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74LVC16373A 数据表 (PDF) - Nexperia B.V. All rights reserved

74LVC16373A Datasheet PDF - Nexperia B.V. All rights reserved
部件名 74LVC16373A
下载  74LVC16373A 下载
文件大小   261.55 Kbytes
  15 Pages
制造商  NEXPERIA [Nexperia B.V. All rights reserved]
网页  https://www.nexperia.com/
标志 NEXPERIA - Nexperia B.V. All rights reserved
功能描述 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

74LVC16373A Datasheet (PDF)

Go To PDF Page 下载 数据表
74LVC16373A Datasheet PDF - Nexperia B.V. All rights reserved

部件名 74LVC16373A
下载  74LVC16373A Click to download

文件大小   261.55 Kbytes
  15 Pages
制造商  NEXPERIA [Nexperia B.V. All rights reserved]
网页  https://www.nexperia.com/
标志 NEXPERIA - Nexperia B.V. All rights reserved
功能描述 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

74LVC16373A 数据表 (HTML) - Nexperia B.V. All rights reserved


74LVC16373A 产品详情

1. General description
The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs.
The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The
devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each
controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the
latches are transparent, a latch output will change each time its corresponding D-input changes.
When nLE is LOW the latches store the information that was present at the inputs a set-up time
preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features and benefits
• Overvoltage tolerant inputs to 5.5 V
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power dissipation
• MULTIBYTE flow-through standard pinout architecture
• Multiple low inductance supply pins for minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold (74LVCH16373A only)
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standards:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C




类似零件编号 - 74LVC16373A

制造商部件名数据表功能描述
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NXP Semiconductors
74LVC16373A PHILIPS-74LVC16373A Datasheet
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1998 Mar 17
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类似说明 - 74LVC16373A

制造商部件名数据表功能描述
logo
NXP Semiconductors
74LVC16373A PHILIPS-74LVC16373A Datasheet
83Kb / 10P
16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State
1998 Mar 17
74LVCH32373A PHILIPS-74LVCH32373A Datasheet
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1999 Nov 24
74LVCH16373A PHILIPS-74LVCH16373A Datasheet
114Kb / 17P
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2003 Dec 08
74LVC_LVCH16373A PHILIPS-74LVC_LVCH16373A_15 Datasheet
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Rev. 8-6 January 2014
74LVC573A PHILIPS-74LVC573A_15 Datasheet
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Rev. 5-19 February 2013
74LVC373A PHILIPS-74LVC373A_15 Datasheet
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Rev. 3-22 November 2012
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74LVC573A-Q100 NEXPERIA-74LVC573A-Q100 Datasheet
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74LVC16373A-Q100 NEXPERIA-74LVC16373A-Q100 Datasheet
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