Nexperia

74LVC16373A; 74LVCH16373A

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

10.1. Waveforms and test circuit

mgu772

Dn input

Qn output

tPHL

tPLH

GND

VI

VM

VM

VM

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that

occur with the output load.

Fig. 6. Input (Dn) to output (Qn) propagation delays

mgu773

LE input

Qn output

tPHL

tPLH

tW

VM

VM

VOH

VI

GND

VOL

VM

VM

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that

occur with the output load.

Fig. 7. Latch enable input (LE) pulse width, and the

latch enable input to output (Qn) propagation

delays

mgu775

tPLZ

tPHZ

outputs

disabled

outputs

enabled

VY

VX

outputs

enabled

Qn output

LOW-to-OFF

OFF-to-LOW

Qn output

HIGH-to-OFF

OFF-to-HIGH

OE input

VI

VOL

VOH

VCC

VM

VM

GND

GND

tPZL

tPZH

VM

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 8. 3-state enable and disable times

mgu774

th

th

tsu

tsu

VM

VM

VI

GND

VI

GND

LE input

Dn input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 9. Data set-up and hold times for the Dn input to the LE input

74LVC_LVCH16373A

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Product data sheet

Rev. 10 — 1 October 2021

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