| 制造商 | 部件名 | 数据表 | 功能描述 |
ON Semiconductor |
NBSG16M
|
81Kb / 12P |
2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
April, 2004 ??Rev. 3 |
|
NB4N11M
|
223Kb / 11P |
3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator
November, 2005 ??Rev. 1 |
|
NB4N527S
|
109Kb / 10P |
3.3V, 2.5Gb/s Dual AnyLevel??to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination
June, 2006 ??Rev. 3 |
|
NB7L11M
|
202Kb / 11P |
2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination
January, 2006 ??Rev. 1 |
|
NB7L14M
|
230Kb / 11P |
2.5V/3.3VDifferential 1:4 Clock/Data Fanout Buffer/Translator with CML Outputs and Internal Termination
January, 2006 ??Rev. 1 |
|
NB7L86M
|
1Mb / 12P |
2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination
January, 2006 ??Rev. 3 |
|
NB7L216
|
264Kb / 12P |
2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination
August, 2006 ??Rev. 2 |
|
NB7L86M
|
1Mb / 12P |
2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination
March, 2012 ??Rev. 7 |
|
NB4L16MMNEVB
|
772Kb / 12P |
2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver/Receiver/Buffer/ Translator with Internal Termination
August, 2016 ??Rev. 4 |
|
NBSG16M
|
143Kb / 12P |
Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
June, 2014 ??Rev. 9 |
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