SUMMARY DESCRIPTION
The M36W0R6030T0 and M36W0R6030B0 combine two memory devices in a Multi-Chip Package: a 64-Mbit, Multiple Bank Flash memory, the M58WR064FT/B, and an 8-Mbit SRAM. Recommended operating conditions do not allow more than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package.

FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
    – 1 die of 64 Mbit (4Mb x 16) Flash Memory
    – 1 die of 8 Mbit SRAM
■ SUPPLY VOLTAGE
    – VDDF = VDDQ = VDDS = 1.7 to 1.95V
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
    – Manufacturer Code: 20h
    – Device Code (Top Flash Configuration): 8810h
    – Device Code (Bottom Flash Configuration): 8811h
■ PACKAGE
    – Compliant with Lead-Free Soldering Processes
    – Lead-Free Versions

FLASH MEMORY
■ PROGRAMMING TIME
    – 8µs by Word typical for Fast Factory Program
    – Double/Quadruple Word Program option
    – Enhanced Factory Program options
■ MEMORY BLOCKS
    – Multiple Bank Memory Array: 4 Mbit Banks
    – Parameter Blocks (Top or Bottom location)
■ SYNCHRONOUS / ASYNCHRONOUS READ
    – Synchronous Burst Read mode: 66MHz
    – Asynchronous/ Synchronous Page Read mode
    – Random Access: 70ns
■ DUAL OPERATIONS
    – Program Erase in one Bank while Read in others
    – No delay between Read and Write operations
■ BLOCK LOCKING
    – All blocks locked at Power-up
    – Any combination of blocks can be locked
    – WPF for Block Lock-Down
■ SECURITY
    – 128-bit user programmable OTP cells
    – 64-bit unique device number
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per BLOCK

SRAM
■ 8 Mbit (512Kb x 16 bit)
■ ACCESS TIME: 70ns
■ LOW VDDS DATA RETENTION: 1.0V
■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS