FUNCTIONAL DESCRIPTION
The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and FIFO #2 each are organized as 256 by 36 bits. The LH543601 is ideal either for wide unidirectional applications or for bidirectional data applications; component count and board area are reduced.

FEATURES
• Fast Cycle Times: 20/25/30/35 ns
• Pin-Compatible and Functionally-Compatible 0.7µ-Technology Replacement for Sharp LH5420
• Two 256 × 36-bit FIFO Buffers
• Full 36-bit Word Width
• Selectable 36/18/9-bit Word Width on Port B
• Independently-Synchronized (‘Fully-Asynchronous’) Operation of Port A and Port B
• ‘Synchronous’ Enable-Plus-Clock Control at Both Ports
• R/W, Enable, Request, and Address Control Inputs are Sampled on the Rising Clock Edge
• Synchronous Request/Acknowledge ‘Handshake’ Capability; Use is Optional
• Device Comes Up Into a Known Default State at Reset; Programming is Allowed, but is not Required
• Asynchronous Output Enables
• Five Status Flags per Port: Full, Almost-Full, Half-Full, Almost-Empty, and Empty
• Almost-Full Flag and Almost-Empty Flag are Programmable
• Mailbox Registers with Synchronized Flags
• Data-Bypass Function
• Data-Retransmit Function
• Automatic Byte Parity Checking
• 8 mA-IOL High-Drive Three-State Outputs with Built-In Series Resistor
• TTL/CMOS-Compatible I/O
• Space-Saving PQFP and TQFP Packages
• PQFP to PGA Package Conversion 1