GENERAL DESCRIPTION
The 16 Meg x 4 DRAMs are high-speed CMOS, dynamic random-access memory devices contain-ing 67,108,864 bits organized in a x4 configuration. The MT4LC16M4A7 and MT4LC16M4T8 are functionally organized as 16,777,216 locations containing four bits each. The 16,777,216 memory locations are arranged in 8,192 rows by 2,048 columns for the MT4LC16M4A7 or 4,096 rows by 4,096 columns for the MT4LC16M4T8.

FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions, and packages
• 13 row, 11 column addresses (A7) 12 row, 12 column addresses (T8)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• FAST-PAGE-MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
• Optional self refresh (S) for low-power data retention