GENERAL DESCRIPTION
The 8 Meg x 8 DRAM is a high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits and designed to operate from 3V to 3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are functionally organized as 8,388,608 locations containing eight bits each.

FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions, and packages
• 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTLcompatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
• Optional self refresh (S) for low-power data retention