AD5273BRJ10-R2 datasheet(3/20 Pages) AD

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AD5273

–3–

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

DYNAMIC CHARACTERISTICS6, 10, 11

Bandwidth –3 dB

BW_1 k

RAB = 1 k, Code = 20H

6000

kHz

BW_10 k

RAB = 10 k, Code = 20H

600

kHz

BW_50 k RAB = 50 k, Code = 20H

110

kHz

BW_100 k RAB = 100 k, Code = 20H

kHz

Total Harmonic Distortion

THDW

V = 1 V rms, RAB = 1 k,

VB = 0 V, f = 1 kHz

0.014

Adjustment Settling Time

tS1

V = 5 V ± 1 LSB Error Band, VB = 0,

Measured at VW

µs

OTP Settling Time12

tS_OTP

V = 5 V ± 1 LSB Error Band, VB = 0,

Measured at VW

400

Power-Up Settling Time –

Post Fuses Blown

tS2

V = 5 V ± 1 LSB Error Band,VB = 0,

Measured at VW

µs

Resistor Noise Voltage

eN_WB

RAB

R = 1 k, f = 1 kHz, Code = 20H

nV/√Hz

√√

RAB

R = 20 k

= 20 k

= 20 k , f = 1 kHz, Code = 20H

nV/√Hz

√√

RAB

R = 50 k

= 50 k

= 50 k , f = 1 kHz, Code = 20H

nV/√Hz

√√

RAB

R = 100 k

= 100 k

= 100 k , f = 1 kHz, Code = 20H

nV/√Hz

√√

INTERFACE TIMING CHARACTERISTICS (applies to all parts

INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 11, 13)

SCL Clock Frequency

fSCL

ffSCL

SCL

400

kHz

tBUF Bus Free Time between

STOP and START

1.3

µs

tHD;STA Hold Time

(repeated START)

After this period, the first clock

pulse is generated.

0.6

µs

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU;STA Setup Time for START

Condition

0.6

µs

tHD;DAT Data Hold Time

0.9

µs

tSU;DAT Data Setup Time

0.1

µs

tF Fall Time of Both SDA and

SCL Signals

0.3

µs

tR Rise Time of Both SDA and

SCL Signals

0.3

µs

tSU;STO Setup Time for STOP

Condition

t10

0.6

µs

NOTES

1Typicals represent average readings at 25°C,VDD = 5 V,VSS = 0 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3VAB

V = VDD,Wiper (VW) = No Connect.

4INL and DNL are measured atVW

INL and DNL are measured atV

INL and DNL are measured atV with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.V

with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.V

with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.V =V

DD and VB = 0 V. DNL specification

limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5Resistor terminals A, B,W have no limitations on polarity with respect to each other.

6Guaranteed by design and not subject to production test.

7Different from operating power supply, power supply for OTP is used one time only.

8Different from operating current, supply current for OTP lasts approximately 400 ms for one time needed only.

9PDISS is calculated from (IDD  VDD). CMOS logic level inputs result in minimum power dissipation.

10 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen.The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

11 All dynamic characteristics use VDD = 5 V.

12 Different from settling time after fuses are blown.The OTP settling time occurs once only.

13 See Figure 1 for location of measured values.

Specifications subject to change without notice.

REV. 0

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