DSP56166ROM datasheet(23/63 Pages) MOTOROLA

部件名	DSP56166ROM

功能描述	16-bit General Purpose Digital Signal Processor

PDF	63 Pages

Scroll/Zoom	100%

制造商	MOTOROLA [Motorola, Inc]

网页	http://www.freescale.com

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23 / 63 page

PRELIMINARY - 6/15/93

DSP56166 Technical Data Sheet

MOTOROLA

Clock Figure 1. External Clock Timing

AC Electrical Characteristics — Other Clock and PLL Operation Timing

Clock Figure 2. Clocking Configurations

a. Maximum DSP operating frequency. See Operating Conditions.

b. An AC coupling capacitor is required on EXTAL if the levels are

out of the normal CMOS level range (VILC>20% of Vdd

or VIHC<70% of Vdd).

Characteristics

Min

Max

Unit

PLL Output frequency

Max

Fosca

MHz

EXTAL Input Clock Amplitude b

Vdd

Vpp

EXTAL

PLL

PLLE=1

PLLE=0

Fosc

ID3-ID0

CLKO

÷ 2

internal phase PH0 at Fosc

CS1-CS0

1000pF

SXFC

VDDS

XFC1

0.01

µF

GNDS

0.1

µF

100K

Ω

÷ 1 to ÷ 16

VCO

PFD

YD7-YD0

÷ 1 to ÷ 256

10nF

Notes:

1. Must be a low leakage capacitor and must be located very close to the SXFC and VDDS pins.

PD3-PD0

÷ 20 to ÷ 215

PS=0

PS=1

DSP56166ROM 数据表(PDF) 23 Page - Motorola, Inc

DSP56166ROM 数据表(HTML) 23 Page - Motorola, Inc

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