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LAN9220 数据表(PDF) 21 Page - Microchip Technology |
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LAN9220 数据表(HTML) 21 Page - Microchip Technology |
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21 / 142 page ![]() 2006-2017 Microchip Technology Inc. DS00002417A-page 21 LAN9220 In Magic Packet mode, the Power Management Logic constantly monitors each frame addressed to the node for a spe- cific Magic Packet pattern. It checks only packets with the MAC’s address or a broadcast address to meet the Magic Packet requirement. The Power Management Logic checks each received frame for the pattern 48h FF_FF_FF_FF_FF_FF after the destination and source address field. Then the Function looks in the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case of a break in the 16 address repetitions, the PMT Function scans for the 48'hFF_FF_FF_FF_FF_FF pattern again in the incoming frame. The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. The device will also accept a multicast frame, as long as it detects the 16 duplications of the MAC address. If the MAC address of a node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet: Frame. Destination Address Source Address ……………FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC It should be noted that Magic Packet detection can be performed when LAN9220 is in the D0 or D1 power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state. 3.6 Checksum Offload Engines (COE) The LAN9220 contains two checksum offload engines, which offload the calculation of the 16-bit checksum for trans- mitted and received Ethernet frames. The functionality of the checksum offload engines is described in the following sections: • Receive Checksum Offload Engine (RXCOE) • Transmit Checksum Offload Engine (TXCOE) 3.6.1 RECEIVE CHECKSUM OFFLOAD ENGINE (RXCOE) The receive checksum offload engine provides assistance to the CPU by calculating a 16-bit checksum for a received Ethernet frame. The RXCOE readily supports the following IEEE802.3 frame formats: • Type II Ethernet frames • SNAP encapsulated frames • Support for up to 2, 802.1q VLAN tags The resulting checksum value can also be modified by software to support other frame formats. The RXCOE has two modes of operation. In mode 0, the RXCOE calculates the checksum between the first 14 bytes of the Ethernet frame and the FCS. This is illustrated in Figure 3-2. FIGURE 3-2: RXCOE CHECKSUM CALCULATION DST SRC T Y P E Frame Data F C S Calculate Checksum |
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