LAN9220 datasheet(36/142 Pages) MICROCHIP

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LAN9220

DS00002417A-page 36

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When the LAN9220 is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the

LAN9220 to the D0 state. Table 7-2, “Power Consumption Device and System Components,” on page 128 and Table 7-

2, “Power Consumption Device and System Components,” on page 128, shows the power consumption values for each

power state.

Note 3-5

When the LAN9220 is in a power saving state, a write of any data to the BYTE_TEST register will

wake-up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit

in the PMT_CTRL register is cleared.

3.10.2.1

D1 Sleep

Power consumption is reduced in this state by disabling clocks to portions of the internal logic as shown in Table 3-10.

In this mode the clock to the internal PHY and portions of the MAC are still operational. This state is entered when the

host writes a '01' to the PM_MODE bits in the Power Management (PMT_CTRL) register. The READY bit in PMT_CTRL

is cleared when entering the D1 state.

Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly enabled via the

WOL_EN and PME_EN bits, the LAN9220 will assert the PME hardware signal upon the detection of the wake-up frame

or magic packet. The LAN9220 can also assert the host interrupt (IRQ) on detection of a wake-up frame or magic packet.

Upon detection, the WUPS field in PMT_CTRL will be set to a 10b.

Note 3-6

The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of

PME_EN.

Note 3-7

Wake-up frame and Magic Packet detection is automatically enabled when entering the D1 state. For

wake-up frame detection, the wake-up frame filter must be programmed before entering the D1 state

(see Section 3.5, "Wake-up Frame Detection," on page 18). If used, the host interrupt and PME signal

must be enabled prior to entering the D1 state.

A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was detected, will return

LAN9220 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check

the READY bit and verify that it is set before attempting any other reads or writes of the device.

Note 3-8

The host must only perform read accesses prior to the ready bit being set.

Once the READY bit is set, the LAN9220 is ready to resume normal operation. At this time the WUPS field can be

cleared.

3.10.2.2

D2 Sleep

In this state, as shown in Table 3-10, all clocks to the MAC and host bus are disabled and the PHY is placed in a reduced

power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY (Mode Control/Status register) must be

set. This places the PHY in the Energy Detect mode. The PM_MODE bits in the PMT_CTRL register must then be set

to 10b. Upon setting the PM_MODE bits, the LAN9220 will enter the D2 sleep state. The READY bit in PMT_CTRL is

cleared when entering the D2 state.

Note 3-9

If carrier is present when this state is entered detection will occur immediately.

If properly enabled via the ED_EN and PME_EN bits, the LAN9220 will assert the PME hardware signal upon detection

of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to a 01b.

Note 3-10

The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the setting of

PME_EN.

A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN9220 to the D0

state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit

and verify that it is set before attempting any other reads or writes of the device. Before the LAN9220 is fully awake from

this state the EDPWRDOWN bit in register 17 of the PHY must be cleared in order to wake the PHY. Do not attempt to

clear the EDPWRDOWN bit until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9220 is ready to

resume normal operation. At this time the WUPS field can be cleared.

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