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ICS952802 数据表(PDF) 10 Page - Integrated Circuit Systems

部件名 ICS952802
功能描述  Programmable Timing Control Hu for P4 processor
PDF  19 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS952802 数据表(HTML) 10 Page - Integrated Circuit Systems

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10
Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
0731—09/18/02
Table2: Divider Ratio Combination Table
Bit
00
01
10
11
MSB
1
2
4
8
00
0000
2
0100
4
1000
8
1100
16
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB
Address
Div
Address
Div
Address
Div
Address
Div
Divider (3:2)
I
2C Table: Output Divider Control Register
Control
Function
Bit 7
AGPDiv3
RW
X
Bit 6
AGPDiv2
RW
X
Bit 5
AGPDiv1
RW
X
Bit 4
AGPDiv0
RW
X
Bit 3
ZCLKDiv3
RW
X
Bit 2
ZCLKDiv2
RW
X
Bit 1
ZCLKDiv1
RW
X
Bit 0
ZCLKDiv0
RW
X
I
2C Table: Output Divider Control Register
Control
Function
Bit 7
AGPINV
AGPPhase Invert
RW
Default
Inverse
X
Bit 6
ZCLKSDINV
ZCLK Phase Invert
RW
Default
Inverse
X
Bit 5
Reserved
Reserved
RW
-
-
X
Bit 4
CPUINV
CPU Phase Invert
RW
Default
Inverse
X
Bit 3
Reserved
Reserved
RW
-
-
X
Bit 2
Reserved
Reserved
RW
-
-
X
Bit 1
Reserved
Reserved
RW
-
-
X
Bit 0
Reserved
Reserved
RW
-
-
X
I
2C Table: Group Skew Control Register
Control
Function
Bit 7
CPUSkw1
RW
1
Bit 6
CPUSkw0
RW
1
Bit 5
Reserved
Reserved
RW
-
-
0
Bit 4
Reserved
Reserved
RW
-
-
0
Bit 3
Reserved
Reserved
RW
-
-
0
Bit 2
ASYNC3
RW
0
Bit 1
ASYNC1
RW
0
Bit 0
ASYNC0
RW
0
See Table 2: Divider Ratio
Combination Table
01
See Table 4: Asynchronous
Frequency Programming
Table
PWD
Type
1
Type
PWD
-
AGP divider ratio can
be configured via these
4 bits individually.
0
-
Byte 17
Pin #
Name
-
-
-
-
-
-
-
Pin #
PWD
-
-
-
Name
Type
0
1
CPU-CPU Skew
Control
-
Byte 18
See Table 3: 4-Steps Skew
Programming Table
-
-
-
-
Async Freq Fix PLL
-
-
Byte 16
Pin #
Name
-
ZCLK divider ratio can
be configured via these
4 bits individually.
See Table 2: Divider Ratio
Combination Table
-
-
-
-



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