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ICS952802 数据表(PDF) 8 Page - Integrated Circuit Systems

部件名 ICS952802
功能描述  Programmable Timing Control Hu for P4 processor
PDF  19 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS952802 数据表(HTML) 8 Page - Integrated Circuit Systems

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8
Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
0731—09/18/02
I
2C Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
-
-
0
Bit 6
BC6
RW
-
-
0
Bit 5
BC5
RW
-
-
0
Bit 4
BC4
RW
-
-
0
Bit 3
BC3
RW
-
-
1
Bit 2
BC2
RW
-
-
1
Bit 1
BC1
RW
-
-
1
Bit 0
BC0
RW
-
-
1
I
2C Table: Watchdog Timer Register
Control
Function
Bit 7
WD7
RW
-
-
0
Bit 6
WD6
RW
-
-
0
Bit 5
WD5
RW
-
-
0
Bit 4
WD4
RW
-
-
1
Bit 3
WD3
RW
-
-
0
Bit 2
WD2
RW
-
-
0
Bit 1
WD1
RW
-
-
0
Bit 0
WD0
RW
-
-
0
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 6
WDEN
Watchdog Enable
RW
Disable
Enable
0
Bit 5
Reserved
Reserved
RW
-
-
0
Bit 4
WD SF4
RW
-
-
0
Bit 3
WD SF3
RW
-
-
0
Bit 2
WD SF2
RW
-
-
0
Bit 1
WD SF1
RW
-
-
0
Bit 0
WD SF0
RW
-
-
1
I
2C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div8
N Divider Bit 8
RW
-
-
X
Bit 6
M Div6
RW
-
-
X
Bit 5
M Div5
RW
-
-
X
Bit 4
M Div4
RW
-
-
X
Bit 3
M Div3
RW
-
-
X
Bit 2
M Div2
RW
-
-
X
Bit 1
M Div1
RW
-
-
X
Bit 0
M Div0
RW
-
-
X
Type
Type
1
Enable
1
0
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
0
0
RW
Disable
Byte 9
Pin #
Name
-
-
-
PWD
1
01
PWD
PWD
Byte 8
Pin #
Name
PWD
-
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
-
-
-
-
-
-
-
-
-
-
-
-
0
Byte 10
Pin #
Bit 7
-M/NEN
M/N Programming
Enable
Name
Type
-
-
-
-
Type
-
-
Writing to these bit will
configure the safe
frequency as Byte 4 bit
2, (7:4)
Byte 11
Pin #
Name
-
The decimal
representation of M Div
(6:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
-
-
-
-
-
-
-
-



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