CDC960

200MHz CLOCK SYNTHESIZER/DRIVER

WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE

SCAS675 – APRIL 2002

4

POST OFFICE BOX 655303

functional block diagram

24/48_SEL

VDD

2 x CPU

SDATA

SMBus

25

48 MHz

PLL

SPREAD

SPECTRUM

24

6 x PCI

33 MHz

(13, 14, 17, 18, 21, 22)

1 x PCI_F

33 MHz

(23)

/2

3 x PCI/LDT

(36, 40)

FS0, FS1, FS2

(1, 45, 48)

1 x USB

48 MHz

(31)

1 x FDC

24/48 MHz

(28)

6

/2

/3

/4

Control

Logic

XIN

3

XOUT

4

Xtal

Oscillator

26

SCLK

CPU

PLL

33/66 MHz

(7, 8, 11)

(200/166/133/100 MHz)

SPREAD

3 x REF

14.318 MHz

(200/166/133/100 MHz)

1

0

44

12

(37, 41)

/2

/2

/5

/6

VDD

VDD

PCI_Stop

PCI/LDT_SEL

LDT_Stop

VDD

VDD

2 x CPU

@ Power Up

@ Power Up