CDC960

200MHz CLOCK SYNTHESIZER/DRIVER

WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE

SCAS675 – APRIL 2002

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POST OFFICE BOX 655303

Desktop Systems

Generate Multiple Output Frequencies

0.5% Downspread for Reduced EMI

Enable and Control

Distribution

– 2 CPU (3.3 V, 180

° shifted pairs,

200/166/133/100 MHz)

– 6 PCI (3.3 V, 33 MHz)

– 1 PCI_F (3.3 V, 33 MHz)

– 3 REF (3.3 V, 14.318 MHz)

– 1 USB (3.3 V, 48 MHz)

– 1 FDC (3.3 V, 24 MHz or 48 MHz)

description

The CDC960 is a clock synthesizer/driver and

buffer that generates CPU, PCI, PCI/LDT, USB,

FDC, and REF system clock signals to support

PCs with an AMD-K8 Clawhammer-class system.

All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided

at the XIN input instead of a crystal. It is recommended to use the bypass mode of the internal oscillator in this

case. Two phase-locked loops (PLLs) are used to generate the host frequencies and 48-MHz clock frequencies.

On-chip loop filters and internal feedback eliminate the need for external components.

The device provides a standard mode (100 kbps) SMBus 1.1 serial interface for device control. The

implementation is as a slave with read and write capability. The device address is specified in the SMBus serial

interface device address table. Both SMBus inputs (SDATA and SCLK) provide integrated pullup resistors

(typically 150 k

Seven 8-bit SMBus registers provide individual enable control for each of the outputs. The controllable outputs

default to enabled at power up and can be placed in a disabled mode with a low-level output when a low-level

control bit is written to the control register. The registers must be accessed in sequential order (i.e., random

access of the registers not supported).

The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz) clock outputs provide low-skew/low-jitter

clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control

inputs FS0, FS1, and FS2 at power-up preset condition.

Copyright

 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†LDT is equivalent to HT66 shown on AMD specification.

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FS0 & REF0

XIN

XOUT

GND

PCI/LDT_SEL

PCI/LDT0

PCI/LDT1

GND

PCI/LDT2

LDT_Stop

PCI0

PCI1

GND

PCI2

PCI3

GND

PCI4

PCI5

PCI_F

PCI_Stop

FS1 & REF1

GND

FS2 & REF2

SPREAD

GNDA

CPU0

CPU0

GND

CPU1

CPU1

GND

GNDF

USB

GND

24/48_SEL & FDC

GND

SDATA

SCLK

DL PACKAGE

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