IIS2DH datasheet(27/49 Pages) STMICROELECTRONICS

部件名	IIS2DH

功能描述	Ultra-low-power high-performance 3-axis accelerometer with digital output for industrial applications

PDF	49 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

27 / 49 page

DocID027668 Rev 2

27/49

IIS2DH

Digital interfaces

5.2.1

SPI read

Figure 7. SPI read protocol

The SPI read command is performed with 16 clock pulses. A multiple byte read command is

performed by adding blocks of 8 clock pulses to the previous one.

bit 0: READ bit. The value is 1.

bit 1: MS bit. When 0, does not increment the address, when 1, increments the address in

multiple reads.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

bit 16-... : data DO(...-8). Further data in multiple byte reads.

Figure 8. Multiple byte SPI read protocol (2-byte example)

SPC

SDI

SD O

DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0

AD5 A D4 AD 3 A D2 AD1 A D0

DO 15 DO 14 DO 13 DO 12 DO 11 DO 10 D O9 D O8

AM10131V1

IIS2DH 数据表(PDF) 27 Page - STMicroelectronics