IIS2DH datasheet(36/49 Pages) STMICROELECTRONICS

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IIS2DH

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DocID027668 Rev 2

7.10

CTRL_REG5 (24h)

7.11

CTRL_REG6 (25h)

Table 37. Self-test mode configuration

ST1

ST0

Self-test mode

Normal mode

Self test 0

Self test 1

11--

Table 38. CTRL_REG5 register

BOOT

FIFO_EN

LIR_INT1

D4D_INT1

LIR_INT2

D4D_INT2

Table 39. CTRL_REG5 description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN

FIFO enable. Default value: 0

(0: FIFO disabled; 1: FIFO enabled)

LIR_INT1

Latch interrupt request on INT1_SRC (31h), with INT1_SRC (31h) register cleared

by reading INT1_SRC (31h) itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

D4D_INT1

4D enable: 4D detection is enabled on INT1 pin when 6D bit on INT1_CFG (30h) is

set to 1.

LIR_INT2

Latch interrupt request on INT2_SRC (35h) register, with INT2_SRC (35h) register

cleared by reading INT2_SRC (35h) itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

D4D_INT2

4D enable: 4D detection is enabled on INT2 pin when 6D bit on INT2_CFG (34h) is

set to 1.

Table 40. CTRL_REG6 register

I2_CLICKen I2_INT1

I2_INT2

BOOT_I2

P2_ACT

- -

H_LACTIVE

Table 41. CTRL_REG6 description

I2_CLICKen

Click interrupt on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

I2_INT1

Interrupt 1 function enable on INT2 pin. Default value: 0

(0: function disabled; 1: function enabled)

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