AD8450ASTZ datasheet(25/42 Pages) AD

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AD8450

Data Sheet

Rev. B | Page 24 of 41

PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER

(PGDA)

Figure 52 is a block diagram of the PGDA, which is used to

monitor the battery voltage. The architecture of the PGDA is a

subtractor amplifier with four selectable inputs: the BVP[0:3]

and BVN[0:3] pins. Each input pair corresponds to one of the

internal gains of the PGDA: 0.2, 0.27, 0.4, and 0.8. These gain

values allow the PGDA to funnel the voltage of up to four 5 V

batteries in series (4S) to a level that can be read by a 5 V ADC.

See Table 6 for information about the gain selection connections.

BVP3

BVREFL

BVP1

BVP0

BVP2

BVN3

BVN2

BVN1

BVN0

100kΩ

80kΩ

100kΩ

100Ω

50kΩ

79.9kΩ

PGDA

–

BVREFH

VREF

BVMEA

Figure 52. PGDA Simplified Block Diagram

The resistors that form the PGDA gain network are laser

trimmed to a matching level better than ±0.1%. This level of

matching minimizes the gain error and gain error drift of the

PGDA while maximizing the CMRR of the PGDA. This match-

ing also allows the controller to set a stable target voltage for the

battery over temperature while rejecting the ground bounce in

the battery negative terminal.

Like the PGIA, the PGDA can also level shift its output voltage

via an internal resistor divider that is tied to the PGDA refer-

ence node. This resistor divider is connected to the BVREFH

and BVREFL pins.

When the BVREFH pin is tied to the VREF pin with the BVREFL

pin grounded, the voltage at the BVMEA pin is increased by 5 mV,

guaranteeing that the output of the PGDA is always positive for

zero differential inputs. Other voltage shifts can be realized by

tying the BVREFH pin to an external voltage source. The gain

from the BVREFH pin to the BVMEA pin is 2 mV/V. For zero

offset, tie the BVREFL and BVREFH pins to ground.

CC AND CV LOOP FILTER AMPLIFIERS

The constant current (CC) and constant voltage (CV) loop filter

amplifiers are high precision, low noise specialty amplifiers with

very low offset voltage and very low input bias current. These

amplifiers serve two purposes:

•

Using external components, the amplifiers implement active

loop filters that set the dynamics (transfer function) of the

CC and CV loops.

•

The amplifiers perform a seamless transition from CC to

CV mode after the battery reaches its target voltage.

Figure 53 is the functional block diagram of the AD8450 CC

and CV feedback loops for charge mode (MODE pin is logic high).

For illustration purposes, the external networks connected to

the loop amplifiers are simple RC networks configured to form

single-pole inverting integrators. The outputs of the CC and CV

loop filter amplifiers are coupled to the VINT pin via an analog

NOR circuit (minimum output selector circuit), such that they can

only pull the VINT node down. In other words, the loop amplifier

that requires the lowest voltage at the VINT pin is in control of

the node. Thus, only one loop amplifier, CC or CV, can be in

control of the system charging control loop at any given time.

ISET

–

CC LOOP

AMPLIFIER

CV LOOP

AMPLIFIER

IVE1

VVE1

ANALOG

NOR

ISVN

BVPx

BVNx

GDA

–

GIA

ISMEA

BVMEA

IBAT

PGIA

PGDA

VVSET

VSET

1×

VCTRL

VCLN

VCLP

VINT

BUFFER

VISET

VBAT

SENSE

RESISTOR

MODE

–

VINT

POWER

CONVERTER

VINT

IOUT

ISVP

VCTRL

I POWER

BUS

MINIMUM

OUTPUT

SELECTOR

V3 < VCTRL < V4

Figure 53. Functional Block Diagram of the CC and CV Loops in Charge Mode (MODE Pin High)

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