AD8450ASTZ datasheet(27/42 Pages) AD

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AD8450

Data Sheet

Rev. B | Page 26 of 41

ISET

–

CC LOOP

AMPLIFIER

CV LOOP

AMPLIFIER

IVE0

VVE0

ANALOG

NOR

ISVN

BVPx

BVNx

GDA

–

GIA

ISMEA

BVMEA

IBAT

PGIA

PGDA

VVSET

VSET

VSETBF

VVP0

1×

VCTRL

VCLN

VCLP

VINT

BUFFER

VISET

VBAT

SENSE

RESISTOR

MODE

–

VINT

POWER

CONVERTER

VINT

IOUT

ISVP

VCTRL

I POWER

BUS

MINIMUM

OUTPUT

SELECTOR

V3 < VCTRL < V4

1×

VSET

BUFFER

Figure 55. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low)

Figure 55 is the functional block diagram of the AD8450 CC

and CV feedback loops for discharge mode (MODE pin is logic

low. In discharge mode, the feedback loops operate in a similar

manner as in charge mode. The only difference is in the CV

loop amplifier, which operates as a noninverting integrator in

discharge mode. For illustration purposes, the external networks

connected to the loop amplifiers are simple RC networks

configured to form single-pole integrators (see Figure 55).

COMPENSATION

In battery formation and test systems, the CC and CV feedback

loops have significantly different open-loop gain and crossover

frequencies; therefore, each loop requires its own frequency

compensation. The active filter architecture of the AD8450 CC

and CV loops allows the frequency response of each loop to be set

independently via external components. Moreover, due to the

internal switches in the CC and CV amplifiers, the frequency

response of the loops in charge mode does not affect the frequency

response of the loops in discharge mode.

Unlike simpler controllers that use passive networks to ground

for frequency compensation, the AD8450 allows the use of feed-

back networks for its CC and CV loop filter amplifiers. These

networks enable the implementation of both PD (Type II) and

PID (Type III) compensators. Note that in charge mode, both

the CC and CV loops implement inverting compensators, whereas

in discharge mode, the CC loop implements an inverting compen-

sator and the CV loop implements a noninverting compensator.

As a result, the CV loop in discharge mode includes an additional

amplifier, VSET buffer, to buffer the VSET node from the feed-

back network (see Figure 55).

VINT BUFFER

The unity-gain amplifier (VINT buffer) is a clamp amplifier

that drives the VCTRL pin. The VCTRL pin is the control

output of the AD8450 and the control input of the power

converter (see Figure 53 and Figure 55). The output voltage

range of this amplifier is bounded by the clamp voltages at

the VCLP and VCLN pins such that

VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V

The reduction in the output voltage range of the amplifier is a

safety feature that allows the AD8450 to drive devices such as the

ADP1972 pulse-width modulation (PWM) controller, whose

input voltage range must not exceed 5.5 V (that is, the voltage at

the COMP pin of the ADP1972 must be below 5.5 V).

MODE PIN, CHARGE AND DISCHARGE CONTROL

The MODE pin is a TTL logic input that configures the AD8450

for either charge or discharge mode. A logic low (VMODE < 0.8 V)

corresponds to discharge mode, and a logic high (VMODE > 2 V)

corresponds to charge mode. Internal to the AD8450, the MODE

pin toggles all SPDT switches in the CC and CV loop amplifiers

and inverts the gain polarity of the PGIA.

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