Data Sheet

VSC7127/VSC7129

Family of Repeater/Retimer and Port

Bypass Circuits for Fibre Channel

VITESSE

SEMICONDUCTOR CORPORATION

Page 6

G52298-0, Rev 4.3

05/01/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Figure 4: REFCLK Timing Waveforms *

Table 2: Reference Clock Requirements

NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements.

Parameters

Description

Min

Typ

Max

Units

Conditions

FR

Frequency Range

105

107

MHz

FO

Frequency Offset

-200

200

ppm

Maximum frequency offset

between transmit and receive

reference clocks on one link

DC

Duty Cycle

35

65

%

Measured at 1.5V

Rise and Fall Time

2.0

ns

Parameters

Description

Min

Typ

Max

Units

Conditions

Output HIGH voltage (TTL)

2.4

V

Output LOW voltage (TTL)

0.5

V

Input HIGH voltage (TTL)

2.0

5.5

V

Input LOW voltage (TTL)

0

0.8

V

Input HIGH current (TTL)

50

500

µA

Input LOW current (TTL)

-500

µA

∆V

OUT75

(1)

TX output differential peak-to-

peak voltage swing

1200

2200

mVp-p

75

Ω to V

∆V

OUT50

(1)

TX output differential peak-to-

peak voltage swing

1000

2200

mVp-p

50

Ω to V

∆V

IN

(1)

Receiver differential peak-to-peak

input Sensitivity RX

400

2600

mVp-p

Supply voltage

3.14

3.47

V

3.3V±5%

Power dissipation

707

902

mW

±2%

Current (all supplies)

215

260

mA

70

mA

REFCLK

NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state.