AD568

REV. A

–3–

ORDERING GUIDE

Linearity

Voltage

Temperature

Error Max

Gain T.C.

Model

l

Package Option

2

Range C@ 25 C

Max ppm/ C

AD568JQ

24-Lead Cerdip (Q-24)

0 to +70

±1/2

±50

AD568KQ

24-Lead Cerdip (Q-24)

0 to +70

±1/4

±30

AD568SQ

24-Lead Cerdip (Q-24)

–55 to +125

±1/2

±50

NOTES

Military Products Databook or current AD568/883B data sheet.

Definitions

LINEARITY ERROR (also called INTEGRAL NONLINEAR-

ITY OR INL): Analog Devices defines linearity error as the

maximum deviation of the actual analog output from the ideal

output (a straight line drawn from 0 to FS) for any bit combina-

tion expressed in multiples of 1 LSB. The AD568 is laser

trimmed to 1/4 LSB (0.006% of FS) maximum linearity error at

+25

°C for the K version and 1/2 LSB for the J and S versions.

DIFFERENTIAL LINEARITY ERROR (also called DIFFER-

ENTIAL NONLINEARITY or DNL): DNL is the measure of

the variation in analog value, normalized to full scale, associated

with a 1 LSB change in digital input code. Monotonic behavior

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD568 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

requires that the differential linearity error not exceed 1 LSB in

the negative direction.

MONOTONICITY: A DAC is said to be monotonic if the out-

put either increases or remains constant as the digital input

increases.

UNIPOLAR OFFSET ERROR: The deviation of the analog

output from the ideal (0 V or 0 mA) when the inputs are set to

all 0s is called unipolar offset error.

BIPOLAR OFFSET ERROR: The deviation of the analog out-

put from the ideal (negative half-scale) when the inputs are set

to all 0s is called bipolar offset error.

18

6

7

8

9

10

11

12

1

2

3

4

5

19

20

23

24

13

14

17

2X

4X

MSB

LSB

PNP

CURRENT

SOURCES

1.4V

BAND-

GAP

REF

THRESHOLD

CONTROL

THRESHOLD

COMMON

LADDER

COMMON

PNP

SWITCHES

DIFFUSED R-2R LADDER

(10 - 20

Ω)

THIN-FILM R-2R LADDER

(100 - 200

Ω)

BIPOLAR

CURRENT

GENERATOR

BURIED

ZENER

REFERENCE

21

22

200

Ω

ANALOG

COMMON

V

CC

I

OUT

REFERENCE

COMMON

1k

Ω

15

16

LOAD RESISTOR

(R

BIPOLAR

OFFSET (I

10V SPAN

RESISTOR

10V SPAN

RESISTOR

I

OUT

I

OUT

AD568

V

EE

Figure 1. Functional Block Diagram

ABSOLUTE MAXIMUM RATINGS

1

REFCOM to LCOM . . . . . . . . . . . . . . . . . +100 mV to –10 V

ACOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mV

THCOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . .

±500 mV

SPANs to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±12 V

Digital Inputs to THCOM . . . . . . . . . . . . . –500 mV to +7.0 V

Voltage Across Span Resistor . . . . . . . . . . . . . . . . . . . . . . 12 V

Logic Threshold Control Input Current . . . . . . . . . . . . . 5 mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mW

Storage Temperature Range

Q (Cerdip) Package . . . . . . . . . . . . . . . . . –65

°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175

°C

Thermal Resistance

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

°C/W

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

°C/W

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

PIN CONFIGURATION