AD568

REV. A

–12–

Circuit Details

Figure 20 shows an approximate timing budget for the A/D con-

verter. If 12 cycles are to be completed in 1

µs, approximately

80 ns is allowed for each cycle. Since the Schottky diodes clamp

the voltage of the summing junction, the DAC settling time ap-

proaches the current-settling value of 35 ns, and hence uses up

less than half the timing budget.

To maintain simplicity, a simple clock is used that runs at a

constant rate throughout the conversion, with a duty cycle of

approximately 90%. If absolute speed is worth the additional

complexity, the clock frequency can be increased as the conver-

sion progresses since the DAC must settle from increasingly

smaller steps.

When seeking a cycle time of less than 100 ns, the delays gener-

ated by the older generation SAR registers become problematic.

Newer, high speed SAR logic chips are becoming available in

the classic 2504 pinout that cuts the logic overhead in half. One

example of this is Zyrel’s ZR2504.

Finding a comparator capable of keeping up with this DAC ar-

rangement is fairly difficult: it must respond to an overdrive of

250

µV (1 LSB) in less than 25 ns. Since no inexpensive com-

parator exists with these specs, special arrangements must be

made. The LT106 comparator provides relatively quick re-

sponse, but requires at least 5 mV of overdrive to maintain this

speed. A discrete preamplifier may be used to amplify the sum-

ming junction voltage to sufficiently overdrive the comparator.

Care must be exercised in the layout of the preamp/comparator

block to avoid introducing comparator instability with the

preamp’s additional gain.

10ns

35ns

15ns

10ns

10ns

0

10ns

20ns

30ns

40ns

50ns

60ns

70ns

80ns

CLOCK

PULSE

START OF NEXT

CLOCK CYCLE

LATCH COMPARATOR

START OF

CLOCK CYCLE

SAR

DELAY

DAC SETTLING

PREAMP

DELAY

COMPARATOR

DELAY

Figure 20. Typical Clock Cycle for a 1

µs SAR A/D

Converter

HIGH-SPEED MULTIPLYING DAC

A powerful use for the AD568 is found in multiplying applica-

tions, where the DAC controls the amplitude of a high-speed

signal. Specifically, using the AD568 as the control voltage

input signal for the AD539 60 MHz analog multiplier and

AD5539 wideband op amp, a high-speed multiplying DAC can

be built.

In the application shown in Figure 21, the AD568 is used in a

buffered voltage output mode to generate the input to the

AD539’s control channel. The speed of the AD568 allows

oversampling of the control signal waveform voltage, thereby

providing increased spectral purity of the amplitude envelope

that modulates the analog input channels.

The AD568 is configured in the unbuffered unipolar output

mode. The internal 200

Ω load resistor creates the 0-1 V FS

output signal, which is buffered and amplified to a 0-3 V range

suitable for the control channel of the AD539.

A 500

Ω input impedance exists at Pin 1, the input channel. To

provide a buffer for the 0-1 V output signal from the AD568

looking into the impedance and to achieve the full-scale range,

the AD841, high-speed, fast settling op amp is included. The

gain of 3 is achieved with a 2 k

Ω resistor configured in follower

mode with a 1 k

Ω pot and 500 Ω resistor. A 20 kΩ pot with

connections to Pins 3, 4 and 12 is provided for offset trim.

The AD539 can accept two separate input signals, each with a

nominal full-scale voltage range of

±2 V. Each signal can then

be simultaneously controlled by the AD568 signal at the com-

mon input channels, Pins 11 and 14, applied to the AD5539 in

a subtracting configuration, provide the voltage output signal:

D

4096

×

2V

(0

≤D ≤4095)

For applications where only a single channel is involved, chan-

D

4096

×

2V

(0

≤D ≤4095)

Some AD539 circuit details: The control amplifier compensa-

300 pF to provide circuit stability. For improved bandwidth and

feedthrough, the feedthrough capacitor between Pins 1 and 2

along the path of the high-speed signal from AD568 should be

kept at a minimum.