AD5246BKS10-R2 datasheet(5/20 Pages) AD

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AD5246

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

I2C INTERFACE TIMING CHARACTERISTICS2, 3

(Specifications Apply to All Parts)

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus Free Time between STOP and START

1.3

µs

tHD;STA Hold Time (Repeated START)

After this period, the first clock pulse is

generated.

0.6

µs

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU;STA Setup Time for Repeated START Condition

0.6

µs

tHD;DAT Data Hold Time

0.9

µs

tSU;DAT Data Setup Time

100

tF Fall Time of Both SDA and SCL Signals

300

tR Rise Time of Both SDA and SCL Signals

300

tSU;STO Setup Time for STOP Condition

t10

0.6

µs

1 Typical specifications represent average readings at 25°C and VDD = 5 V.

2 Guaranteed by design and not subject to production test.

3 See timing diagrams (

, Figu

) for locations of measured values.

Figure 25

re 26 Figure 27

Rev. 0 | Page 5 of 20

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