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AD5246

TERMINAL VOLTAGE OPERATING RANGE

The AD5246 VDD and GND power supply defines the boundary

conditions for proper 3-terminal digital potentiometer

operation. Supply signals present on terminals B and W that

exceed VDD or GND will be clamped by the internal forward

biased diodes (see

Figure 32

Figure 32. Maximum Terminal Voltages Set by VDD and GND

igure 32

VDD

GND

MAXIMUM OPERATING CURRENT

At low code values, the user should be aware that due to low

resistance values, the current through the RDAC may exceed

the 5 mA limit. In F

, a 5 V supply is placed on the wiper,

and the current through terminals W and B is plotted with

respect to code. A line is also drawn denoting the 5 mA current

limit. Note that at low code values (particularly for the 5 kΩ and

10 kΩ options), the current level increases significantly. Care

should be taken to limit the current flow between W and B in

this state to a maximum continuous current of 5 mA and a

maximum pulse current of no more than 20 mA. Otherwise,

degradation or possible destruction of the internal switch

contacts can occur.

igure 33

Figure 33. Maximum Operating Current

CODE (Decimal)

0.01

0.10

1.00

10.00

112

128

100.00

5mA CURRENT LIMIT

RAB = 5kΩ

RAB = 10kΩ

RAB = 100kΩ

RAB = 50kΩ

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance at

terminals B and W (see F

), it is important to power

VDD/GND before applying any voltage to terminals B and W;

otherwise, the diode will be forward biased such that VDD will be

powered unintentionally and may affect the rest of the user’s

circuit. The ideal power-up sequence is in the following order:

GND, VDD, digital inputs, and then VB/VW. The relative order of

powering VB and VW and the digital inputs is not important as

long as they are powered after VDD/GND.

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ a compact, minimum lead-length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Similarly, it is a good practice to bypass the power supplies with

quality capacitors for optimum stability. Supply leads to the

device should be bypassed with 0.01 µF to 0.1 µF disc or chip

ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or

electrolytic capacitors should also be applied at the supplies to

minimize any transient disturbance and low frequency ripple

(see

). Note that the digital ground should also be

joined remotely to the analog ground at one point to minimize

the ground bounce.

Figure 34

Figure 34. Power Supply Bypassing

AD5246

VDD

GND

µF

0.1

µF

VDD

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