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AC101L-DS02-R 数据表(PDF) 24 Page - Broadcom Corporation. |
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AC101L-DS02-R 数据表(HTML) 24 Page - Broadcom Corporation. |
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24 / 54 page ![]() AC101L Preliminary Data Sheet 8/9/04 B roa dcom Co rpo rat ion Page 14 TP PHY Register Summary Document AC101L-DS06-R REGISTER 0: CONTROL REGISTER REGISTER 1: STATUS REGISTER Table 5: Register 0: Control Register Bit Name Description Mode Default 0.15 Reset 1 = PHY reset. This bit is self-clearing. RW/ SC 0 0.14 Loopback 1 = Enable loopback mode. This loops back TXD to RXD and ignores all of the activity on the cable media. 0 = Normal operation. RW 0 0.13 Speed Select 1 = 100 Mbps. 0 = 10 Mbps. Default value: SPD100 RW Set by SPD100 0.12 ANEN Enable 1 = Enable the auto-negotiate process (overrides 0.13 and 0.8). 0 = Disable the auto-negotiate process. Mode selection is controlled via bit 0.8, 0.13. Default value: ANEN RW Set by ANEN 0.11 Power Down 1 = Power down. All blocks except for SMI will be turned off. Setting PDOWN pin (24) to LOW will achieve the same result. 0 = Normal operation. RW 0 0.10 Isolate 1 = N/A. 0 = Normal operation. RW 0 0.9 Restart ANEN 1 = Restart auto-negotiation process. 0 = Normal operation. RW/ SC 0 0.8 Duplex Mode 1 = Full-duplex operation. 0 = Half-duplex operation. Default value: !ANEN && DUPLEX RW See descriptio n 0.7 Collision Test 1 = Enable collision test that issues the COL signal in response to the assertion of the TXEN signal. Collision test is disabled if the PCSBP pin is high. Collision test is enabled regardless of the duplex mode. 0 = Disable COL test. RW 0 0.[6:0 ] Reserved – RW 0000000 Table 6: Register 1: Status Register Bit Name Description Mode Default 1.15 100BASE-T4 Permanently tied to zero; indicates no 100BASE-T4 capability. RO 0 1.14 100BASE-TX Full-Duplex 1 = 100BASE-TX full-duplex capable. 0 = Not 100BASE-TX full-duplex capable. Default value: SPD100 && DUPLEX RO See description |
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