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AC101L-DS02-R 数据表(PDF) 31 Page - Broadcom Corporation.

部件名 AC101L-DS02-R
功能描述  Ultra Low-Power 10/100 Ethernet Transceiver with Auto-MDIX
PDF  54 Pages
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制造商  BOARDCOM [Broadcom Corporation.]
网页  http://www.broadcom.com
标志 BOARDCOM - Broadcom Corporation.

AC101L-DS02-R 数据表(HTML) 31 Page - Broadcom Corporation.

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Preliminary Data Sheet
AC101L
8/9/04
B roa dcom Co rpo rat ion
Document
AC101L-DS06-R
TP PHY Register Summary
Page 21
REGISTER 21: RECEIVE ERROR COUNTER
REGISTER 22: POWER MANAGEMENT REGISTER
REGISTER 23: OPERATION MODE REGISTER
Table 18: Register 21: Receive Error Counter
Bit
Name
Description
Mode
Default
21.[15:0]
RXER Counter
Counts Receive Error events.
RO
0
Table 19: Register 22: Power Management Register
Bit
Name
Description
Mode
Default
22.[15:14]
Reserved
–
RO
00
22.13
PD_PLL
1 = PLL circuit powers down.
RO
X
22.12
PD_EQUAL
1 = Equalizer circuit powers down.
RO
X
22.11
PD_BT_RCVR
1 = 10BASE-T receiver powers down.
RO
X
22.10
PD_LP
1 = Link pulse receiver powers down.
RO
X
22.9
PD_EN_DET
1 = Energy-detect circuit powers down.
RO
X
22.8
PD_FX
1 = FX circuit powers down.
RO
X
22.[7:6]
Reserved
–
RW
00
22.5
MSK_PLL
0 = Forces PLL circuit to power up.
1 = PLL circuit auto power-down.
RW
1
22.4
MSK_EQUAL
0 = Forces equalizer circuit to power up.
RW
X
22.3
MSK_BT_RCVR
0 = Forces 10BASE-T receiver to power up.
RW
X
22.2
MSK_LP
0 = Forces link pulse receiver to power up.
RW
X
22.1
MSK_EN_DET
0 = Forces energy-detect circuit to power up.
RW
X
22.0
MSK_FX
0 = Forces FX circuit to power up.
RW
X
Table 20: Register 23: Operation Mode Register
Bit
Name
Description
Mode
Default
23.[15:14]
Reserved
–
23.13
Clk_rclk_save
1 = Sets rclk save mode. Rclk shuts off after 64 cycles of each
packet.
0
23.12
Reserved
–
23.11
Scramble
Disable
1 = Disables scrambler.
0 = Enables scrambler.
RW
0
23.10
Reserved
–
RW
0
23.9
Pcsbp
1 = Enables PCS bypass mode.
0 = Disables PCS bypass mode.
RW
0
23:8
Reserved
–
RW
0
23.7
Auto-MDIX
disable
0 = Auto-MDIX mode.
1 = Disable Auto-MDIX mode.
RW
0



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