DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

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LIST OF FIGURES

Figure 1-1. External Connections ............................................................................................................ 7

Figure 2-1. 4-Port Unchannelized DS3/E3 Card ...................................................................................... 7

Figure 3-1. Hardware Mode Block Diagram............................................................................................. 8

Figure 3-2. CPU Bus Mode Block Diagram.............................................................................................. 9

Figure 5-1. Status Register Logic .......................................................................................................... 16

Figure 6-1. Receiver Jitter Tolerance..................................................................................................... 24

Figure 7-1. E3 Waveform Template....................................................................................................... 27

Figure 7-2. DS3 AIS Structure ............................................................................................................... 28

Figure 8-1. PRBS Output with Normal RCLK Operation ........................................................................ 29

Figure 8-2. PRBS Output with Inverted RCLK Operation....................................................................... 29

Figure 9-1. Jitter Attenuation/Jitter Transfer........................................................................................... 30

Figure 12-1. JTAG Block Diagram ......................................................................................................... 32

Figure 12-2. JTAG TAP Controller State Machine ................................................................................. 33

Figure 13-1. Transmitter Framer Interface Timing Diagram ................................................................... 38

Figure 13-2. Receiver Framer Interface Timing Diagram ....................................................................... 39

Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed) ...................................................................... 41

Figure 13-4. CPU Bus AC Timing Diagram (Multiplexed)....................................................................... 43

Figure 13-5. JTAG Timing Diagram ....................................................................................................... 45

Figure 14-1. DS3151 Hardware Mode Pin Assignment.......................................................................... 51

Figure 14-2. DS3151 CPU Bus Mode Pin Assignment .......................................................................... 52

Figure 14-3. DS3152 Hardware Mode Pin Assignment.......................................................................... 53

Figure 14-4. DS3152 CPU Bus Mode Pin Assignment .......................................................................... 54

Figure 14-5. DS3153 Hardware Mode Pin Assignment.......................................................................... 55

Figure 14-6. DS3153 CPU Bus Mode Pin Assignment .......................................................................... 56

Figure 14-7. DS3154 Hardware Mode Pin Assignment.......................................................................... 57

Figure 14-8. DS3154 CPU Bus Mode Pin Assignment .......................................................................... 58