DS75451M datasheet(5/16 Pages) NSC

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DC Test Circuits

TLF5824 – 15

Both inputs are tested simultaneously

FIGURE 1 VIH VOL

TLF5824 – 16

Each input is tested separately

FIGURE 2 VIL VOH

TLF5824 – 17

Each input is tested separately

FIGURE 3 VI IIL

TLF5824 – 18

Each input is tested separately

FIGURE 4 II IIH

TLF5824 – 19

Each input is tested separately

FIGURE 5 IOS

TLF5824 – 20

Both gates are tested simultaneously

FIGURE 6 ICCH ICCL

TLF5824 – 21

Circuit

Under

Input

Test

Other

Input

Output

Apply

Measure

DS55451

VIH

VOH

IOH

VIL

VCC

IOL

VOL

DS55452

VIH

IOL

VOL

VIL

VCC

VOH

IOH

DS55453

VIH

Gnd

VOH

IOH

VIL

IOL

VOH

DS55454

VIH

Gnd

IOL

VOL

VIL

VOH

IOH

FIGURE 7 VIH VIL IOH VOL

Note A

Each input is tested separately

Note B

When testing DS55453DS75453

DS55454DS75454 input not

under test is grounded

For all other circuits it is at 45V

TLF5824 – 22

FIGURE 8 VI VIL

Each input is tested separately

TLF5824 – 23

FIGURE 9 II IIH

Both gates are tested simultaneously

TLF5824 – 24

FIGURE 10 ICCH ICCL for AND NAND Circuits

Both gates are tested simultaneously

TLF5824 – 25

FIGURE 11 ICCH ICCL for OR NOR Circuits

DS75451M 数据表(PDF) 5 Page - National Semiconductor (TI)

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