AD5247

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

positive, voltage across A–B, W–A, and W–B can be at either

polarity.

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across terminal AB divided by the 128 positions

of the potentiometer divider. The general equation defining the

voltage applied to terminals A and B is

A

W

V

D

D

V

128

)

(

=

(3)

For a more accurate calculation, which includes the effect of

A

AB

WB

W

V

R

D

R

D

V

)

(

)

(

=

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike in

rheostat mode, the output voltage in divider mode is dependent

the absolute values. Therefore, the temperature drift reduces to

15 ppm/°C.

The first byte of the AD5247 is a slave address byte (see

and

). It has a 7-bit slave address and a R/W bit. The

seven MSBs of the slave address are 0101110 followed by 0 for a

write command or 1 to place the device in read mode.

Table 5

able 5

Table 6

1.

The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see

). The

following byte is the slave address byte, which consists of

the 7-bit slave address followed by an R/W bit (this bit

determines whether data will be read from or written to

the slave device).

Figure 32

igure 32

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its serial register. If the R/W bit is high, the master will read

from the slave device. On the other hand, if the R/W bit is

low, the master will write to the slave device.

2.

In write mode, after acknowledgement of the slave address

byte, the next byte is the data byte. Data is transmitted over

the serial bus in sequences of nine clock pulses (eight data

bits followed by an acknowledge bit). The transitions on

the SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see T

).

3.

In read mode, after acknowledgment of the slave address

byte, data is received over the serial bus in sequences of

nine clock pulses (a slight difference from write mode,

where eight data bits are followed by an acknowledge bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during the

high period of SCL (see

).

Figure 33

igure 33

4.

When all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master will pull the SDA

line high during the tenth clock pulse to establish a STOP

condition (see F

). In read mode, the master will

issue a No Acknowledge for the ninth clock pulse (i.e., the

SDA line remains high). The master will then bring the

SDA line low before the tenth clock pulse, which goes high

to establish a STOP condition (see F

).

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing the part only

once. For example, after the RDAC has acknowledged its slave

address in the write mode, the RDAC output will update on

each successive byte. If different instructions are needed, the

write/read mode has to start again with a new slave address and

data byte. Similarly, a repeated read function of the RDAC is

also allowed.

Rev. 0 | Page 14 of 20