AD5247

A

W

GND

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

While most legacy systems may be operated at one voltage, a

new component may be optimized at another. When two

systems operate the same signal at two different voltages, proper

level shifting is needed. For instance, one can use a 3.3 V

shifting scheme is needed to enable a bidirectional communi-

cation so that the setting of the digital potentiometer can be

shows one

of the implementations. M1 and M2 can be any N channel

threshold FETs such as the FDV301N.

igure 35

Figure 35. Level Shifting for Operation at Different Potentials

AD5247

SDA1

SCL1

D

G

3.3V

5V

S

M1

SCL2

SDA2

G

S

M2

D

ESD PROTECTION

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures shown in

and

.

This applies to the digital input pins SDA and SCL.

Figure 36

Figure 36. ESD Protection of Digital Pins

Figure 37

Figure 37. ESD Protection of Resistor Terminals

LOGIC

340

Ω

GND

A,W

GND

TERMINAL VOLTAGE OPERATING RANGE

conditions for proper 3-terminal digital potentiometer

operation. Supply signals present on terminals A and W that

biased diodes (see

).

Figure 38

igure 38

MAXIMUM OPERATING CURRENT

At low code values, the user should be aware that due to low

resistance values, the current through the RDAC may exceed

the 5 mA limit. In F

, a 5 V supply is placed on the wiper,

and the current through terminals W and B is plotted with

respect to code. A line is also drawn denoting the 5 mA current

limit. Note that at low code values (particularly for the 5 kΩ and

10 kΩ options), the current level increases significantly. Care

should be taken to limit the current flow between W and B in

this state to a maximum continuous current of 5 mA and a

maximum pulse current of no more than 20 mA. Otherwise,

degradation or possible destruction of the internal switch

contacts can occur.

igure 39

Figure 39. Maximum Operating Current

CODE (Decimal)

0

0.01

0.10

1.00

10.00

16

32

48

64

80

96

112

128

100.00

5mA CURRENT LIMIT

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance at

terminals A and W (see F

), it is important to power

powered unintentionally and may affect the rest of the user’s

circuit. The ideal power-up sequence is in the following order:

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