AD8027/AD8028

Rev. B | Page 17 of 24

In the event that the crossover region cannot be avoided, spe-

cific attention has been given to the input stage to ensure con-

stant transconductance and minimal offset in all regions of

operation. The regions are: PNP input pair running, NPN input

pair running, and both running at the same time (in the

200 mV crossover region). Maintaining constant transconduc-

tance in all regions ensures the best wideband distortion per-

formance when going between these regions. With this tech-

nique, the AD8027/AD8028 can achieve greater than 80 dB

SFDR for a 2 V p-p, 1 MHz, G = +1 signal on ±1.5 V supplies.

Another requirement in achieving this level of distortion is the

offset of each pair must be laser trimmed to achieve greater

than 80 dB SFDR, even for low frequency signals.

Output Stage

The AD8027/AD8028 uses a common-emitter output structure

to achieve rail-to-rail output capability. The output stage is

designed to drive 50 mA of linear output current, 40 mA within

200 mV of the rail, and 2.5 mA within 35 mV of the rail.

Loading of the output stage, including any possible feedback

network, will lower the open-loop gain of the amplifier. Refer to

Figure 49 for the loading behavior. Capacitive load can degrade

the phase margin of the amplifier. The AD8027/AD8028 can

drive up to 20 pF, G = +1 as seen in Figure 10. A small (25 Ω to

load is to exceed 20 pF for a gain of 1. Increasing the closed-

loop gain will increase the amount of capacitive load that can be

driven before a series resistor will need to be included.

DC Errors

The AD8027/AD8028 uses two complementary input stages to

achieve rail-to-rail input performance, as mentioned in the

Input Stage section. To use the dc performance over the entire

common-mode range, the input bias current and input offset

voltage of each pair must be considered.

Referring to Figure 56, the output offset voltage of each pair is

calculated by













+

=

G

F

G

PNP

OS

OUT

PNP

OS

R

R

R

V

V

,

,

,

,













+

=

G

F

G

NPN

OS

OUT

NPN

OS

R

R

R

V

V

,

,

,

where the difference of the two will be the discontinuity experi-

enced when going through the crossover region. The size of the

discontinuity is defined as

(

)













+

×

−

=

G

F

G

NPN

OS,

PNP

OS,

DIS

R

R

R

V

V

V

Using the crossover select feature of the AD8027/AD8028 helps

to avoid this region. In the event that the region cannot be

this effect.

Because the input pairs are complementary, the input bias

current will reverse polarity when going through the cross

over region shown in Figure 37. The offset between pairs is

described by

()

















−













+

×

−

=

−

F

G

F

G

S

NPN

B,

PNP

B,

NPN

OS,

PNP

OS,

R

R

R

R

R

I

I

V

V

is the input bias current of either input when the PNP

eliminated. It is strongly recommended to balance the imped-

ances in this manner when traveling through the crossover

region to minimize the dc error and distortion. As an example,

assuming the PNP input pair has an input bias current of 6 µA

and the NPN input pair has an input bias current of –2 µA, a

200 µV shift in offset will occur when traveling through the

In addition to the input bias current shift between pairs, each

input pair has an input bias current offset that will contribute to

the total offset in the following manner

F

B

G

F

G

S

B

OS

R

I

R

R

R

R

I

V

−

+

−













+

=

∆

+–

+–

+

–

SELECT

–V

+V

–

+

AD8027/

AD8028

03327-A-055

Figure 56. Op Amp DC Error Sources