AM29PL320DB60RWPI datasheet(21/50 Pages) SPANSION

21 / 50 page

October 2, 2003

Am29PL320D

Figure 1.

SecSi Sector Protect Verify

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using VID.

If the system asserts VIL on the WP# input, the device

disables program and erase functions in Sector 0 (for

bottom boot) or Sector 18 (for top boot) independently

of whether those sectors were protected or unpro-

tected using the method described in “Sector Protec-

tion/Unprotection”.

If the system asserts VIH on the WP# input, the device

reverts to whether Sector 0 or 18 was last set to be

protected or unprotected. That is, sector protection or

unprotection for that sector depends on whether they

were last protected or unprotected using the method

described in “Sector Protection/Unprotection”.

Note that the WP# input must not be left floating or un-

connected; inconsistent behavior of the device may re-

sult.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 13 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during VCC power-up

and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets. Subsequent writes are ignored

until VCC is greater than VLKO. The system must pro-

vide the proper signals to the control inputs to prevent

unintentional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. Table 13 defines the valid register com-

mand sequences.

Note that writing incorrect address

and data values or writing them in the improper se-

quence may place the device in an unknown state. A

reset command is required to return the device to nor-

mal operation.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

VIH or VID

Wait 1

µs

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

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