SiC521, SiC521A

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Vishay Siliconix

S15-0170-Rev. B, 09-Feb-15

5

Document Number: 62989

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-state Function

The PWM input receives the PWM control signal from the VR

controller IC. The PWM input is designed to be compatible

with standard controllers using two state logic (H and L) and

advanced controllers that incorporate tri-state logic (H, L

and tri-state) on the PWM output. For two state logic, the

PWM input operates as follows. When PWM is driven above

high-side is turned OFF and the low-side is turned ON. For

tri-state logic, the PWM input operates as previously stated

for driving the MOSFETs when PWM is logic high and logic

low. However, there is a third state that is entered as the

PWM output of tri-state compatible controller enters its high

impedance state during shut-down. The high impedance

state of the controller’s PWM output allows the SiC521 and

SiC521A to pull the PWM input into the tri-state region (see

definition of PWM logic and Tri-State, fig. 4). If the PWM

input stays in this region for the Tri-state Hold-Off Period,

OFF. The function allows the VR phase to be disabled

without negative output voltage swing caused by inductor

ringing and saves a Schottky diode clamp. The PWM and

tri-state regions are separated by hysteresis to prevent false

triggering.

The

SiC521A

incorporates

PWM

voltage

thresholds that are compatible with 3.3 V logic and the

SiC521 thresholds are compatible with 5 V logic.

Diode Emulation Mode (ZCD_EN#)

When ZCD_EN# pin is logic low and PWM signal switches

low, GL is forced ON (after normal BBM time). During this

time, it is under control of the ZCD (zero crossing detect)

comparator. If, after the internal blanking delay, the inductor

current becomes zero, the low-side is turned OFF. This

improves light load efficiency by avoiding discharge of

output capacitors. If PWM enters tri-state, then device will

go into normal tri-state mode after tri-state delay. The GL

output will be turned OFF regardless of Inductor current, this

is an alternative method of improving light load efficiency by

reducing switching losses.

This is the power input to the drain of the high-side power

MOSFET. This pin is connected to the high power

intermediate BUS rail.

This is the output applied to the power inductor and output

filter to deliver the output for the buck converter. The PHASE

is to be used exclusively as the return pin for the BOOT

capacitor. A 20 k

Ω resistor is connected between GH and

PHASE to provide a discharge path for the HS MOSFET in

inductance effects between these two pins should not

exceed 0.5 V.

the bias supply for the gate drivers. It is recommended to

separate these pins through a resistor. This creates a low

pass filtering effect to avoid coupling of high frequency gate

drive noise into the IC.

Bootstrap Circuit (BOOT)

The internal bootstrap diode and an external bootstrap

capacitor form a charge pump that supplies voltage to the

BOOT pin. An integrated bootstrap diode is incorporated so

that only an external capacitor is necessary to complete the

bootstrap circuit. Connect a boot strap capacitor with one

leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC521 and SiC521A have an internal adaptive logic to

avoid shoot through and optimize dead time. The shoot

through protection ensures that both high-side and low-side

MOSFETs are not turned ON at the same time. The adaptive

dead time control operates as follows. The high-side and

low-side gate voltages are monitored to prevent the

MOSFET turning ON from tuning ON until the other

MOSFET's gate voltage is sufficiently low (< 1 V). Built in

delays also ensure that one power MOSFET is completely

OFF, before the other can be turned ON. This feature helps

to adjust dead time as gate transitions change with respect

to output current and temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate

drive, holding high-side and low-side MOSFET gates low,

until the supply voltage rail has reached a point at which

the logic circuitry can be safely activated. The SiC521 and

SiC521A also incorporate logic to clamp the gate drive

signals to zero when the UVLO falling edge triggers the

shutdown of the device. As an added precaution, a 20 k

Ω

resistor is connected between GH and PHASE to provide a

discharge path for the HS MOSFET.