SiC521, SiC521A

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Vishay Siliconix

S15-0170-Rev. B, 09-Feb-15

10

Document Number: 62989

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

as close as possible to the IC. It is recommended to

connect two capacitors separately.

instantaneous driver current for low side MOSFET during

switching cycle.

a large plane to reduce parasitic inductance.

Step 4: BOOT Resistor and Capacitor Placement

1. The components need to be placed as close as possible

to IC, directly between PHASE (pin 5) and BOOT (pin 4).

2. To reduce parasitic inductance, chip size 0402 can be

used.

Step 5: Signal Routing

1. Route the PWM and ZCD_EN# signal traces out of the

top left corner next to pin 1.

2. The PWM signal is an important signal, both signal and

return traces should not cross any power nodes on any

layer.

3. It is best to “shield” these traces from power switching

integrity.

4. GL (pin 19) has been connected with GL pad (pin 24)

internally.

Step 6: Adding Thermal Relief Vias

pads to utilize inner layers for high-current and thermal

dissipation.

2. To achieve better thermal performance, additional vias

place vias on this pad.

4. 8 mil vias for pads and 10 mils vias for planes are the

optimal via sizes. Vias on pad may drain solder during

assembly and cause assembly issues. Consult with the

assembly house for guidelines.

Cboot

Rboot