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and a resistive contribute given by the ESR of the capacitor and which is equal to

∆VC fixes the value for C7 while ∆VESR limits the ESR of the capacitor.Usually the capacitor is chosen so that

allowed voltage ripple on Vo then it should result:

More often the minimum value of C7 is imposed by other considerations such as to get a good dynamic behav-

iour of the output voltage in case of large load variations.

Free-wheeling diode

Compensation Network

In continuous mode, the voltage controlled buck converter showes two poles due to the output LC filter and one

zero due to the ESR of the output capacitor. The suggested compensation network introduces two zeros and

two poles:

– the zeros compensate the double poles of the LC filter

– one pole compensates the zero due to ESR of the output capacitor

– the second pole is nominally located in the origin which means an infinite gain at frequency null. In

the reality the DC value of the closed loop gain can not be greater than the DC value of the EA open

loop gain and the pole is located at very low frequency.

The values for the components of the compensation network can be fixed when the inductor L1 and the output

capacitor C7 are chosen.

The necessary steps are following:

Usually

2.Calculate the high frequency error amplifier gain

3.Chose R3 and calculate

The value for R3 has not to be very high (for example 10K

Ω) so to limit the error due to an error amplifier input

offset current.

∆V

c

∆I

Lm ax

,

8C7 f

sw m in

,

⋅⋅

---------------------------------------

=

∆V

ESR

ESR

∆I

Lm a x

,

⋅

=

V

ri ppl e

∆V

c

2

∆V

ES R

2

+

≥

f

c

0.1 f

sw,min

⋅

=

G

c

0.25 f

c

2

π

L1

ESR

-------------

⋅⋅ ⋅ ⋅

=

C8

2

L1 C7

⋅

R3

-----------------------

⋅

=