LP3209-01

Jul.-2017

www.lowpowersemi.com

Page 9 of 10

Preliminary Datasheet

LP3209

Layout Guidance

When laying out the PC board, the following layout guideline

should be followed to ensure proper operation of the LP3209:

1. The power traces, including the GND trace, the SW trace

and the IN trace should be kept short, direct and wide to allow

large current flow. The L1 connection to the SW pins should

be as short as possible. Use several VIA pads when routing

between layers.

2. The input capacitor (C1) should connect as closely as

possible to VIN (Pin 2) and GND to get good power filtering.

3. Keep the switching node, SW away from the sensitive FB

node.

4. The feedback trace or OUT pin should be separate from

any power trace and connect as closely as possible to the

load point.

Sensing along a high-current load trace will degrade DC load

regulation. If external feedback resistors are used, they

should be placed as closely as possible to the FB pin (Pin5) to

minimize the length of the high impedance feedback trace.

5. The output capacitor C2 and L1 should be connected as

closely as possible. The connection of L1 to the SW pin

should be as short as possible and there should not be any

signal lines under the inductor.

6. The resistance of the trace from the load return to PGND

should be kept to a minimum. This will help to minimize any

error in DC regulation due to differences in the potential of the

internal signal ground and the power ground.