LP28301-02

Mar.-2017

www.lowpowersemi.com

Page 2 of 9

Preliminary Datasheet

LP28301

Pin Description

Pin

Name

Description

1

VDDP

Internal LDO output. Connect a decoupling 4.7µF capacitor to GNDP.

2

BST

Positive supply for the high side driver. A 1µF capacitor should be placed between BST and LX.

3

LX

Switching Node Connection.

4

HDR

High side drive gate.

5

GNDP

Ground for Power section.

6

LDR

Low side drive gate.

7

STAT

Indicates charge status. Active low when charging is on. STAT will blink with timeout, NTC fault.

8

NTC

Connect a 10K NTC resistor to GNDA, 100μA(constant current source) current output from NTC

pin.

9

COMP

Compensation pin, a 2.2nF ceramic capacitor is needed from COMP to GNDA.

10

REG

Input voltage feedback for the input voltage regulation loop. Connect to tap of an external resistor

divider from VIN to GNDA to program the input voltage regulation. Once the voltage at REG pin

drops to the inner threshold, the charge current is reduced to maintain the input voltage at the

regulation value.

12

ISET

11,13,16,29

GNDA

Ground for the analog circuits.

14

FULL

Battery full indication pin, active low.

15

VB

Programmable battery-full voltage. Connect to GND for 4.35V, leave floating to 4.2V, and connect

to VDDA for 4.3V.

17

CE

Charge enable pin. Active high.

19

IREF

Current reference generator. A 100k resistor connect to GNDA, internal voltage reference is 1V.

18,20

VDDA

Power supply for the internal analog circuit.

21,22

VBAT

Battery charger output and battery voltage sense pin. Connect to battery cell.

23,24

VSNS

Connect the internal sense resistor to protect the battery.

25,2627,28

VIN

USB or adapter input.