11

 2004 Semtech Corp.

www.semtech.com

SC1485

POWER MANAGEMENT

Stability Considerations

Unstable operation shows up in two related but dis-

tinctly different ways: double pulsing and fast-feedback

loop instability.

Double-pulsing occurs due to noise on the output or be-

cause the ESR is too low, causing not enough voltage

ramp in the output signal. This causes the error amplifier

to trigger prematurely after the 400ns minimum off-time

has expired. Double-pulsing will result in higher ripple

voltage at the output, but in most cases is harmless.

However, in some cases double-pulsing can indicate the

presence of loop instability, which is caused by insuffi-

cient ESR. One simple way to solve this problem is to add

some trace resistance in the high current output path. A

side effect of doing this is output voltage droop with load.

Another way to eliminate doubling-pulsing is to add a 10pF

capacitor across the upper feedback resistor divider

network. This is shown below in Figure 5, by capacitor

C4 in the schematic. This capacitance should be left out

until confirmation that double-pulsing exists. Adding this

capacitance will add a zero in the transfer function and

should eliminate the problem. It is best to leave a spot

on the PCB in case it is needed.

FBK

+5V

+

C1

1

2

3

4

5

6

7

PGND

DL

VDDP

ILIM

LX

DH

BST

+VIN

R2

C2

Q2

L1

Q1

R1

0.5V - 5.5V

C4

10pF

D2

D1

R3

+

C3

FIGURE 5

Loop instability can result in oscillations at the output

after line or load perturbations that can trip the overvolt-

age protection latch or cause the output voltage to fall

below the tolerance limit.

The best way for checking stability is to apply a zero to

full load transient and observe the output voltage ripple

envelope for overshoot and ringing. Over one cycle of

ringing after the initial step is sign that the ESR should

be increased.

Applications Information (Cont.)

SC1485 ESR Requirements

The constant on-time control used in the SC1485

regulates the ripple voltage at the output capacitor. This

signal consists of a term generated by the output ESR of

the capacitor and a term based on the increase in voltage

across the capacitor due to charging and discharging

during the switching cycle. The minimum ESR is set to

generate the required ripple voltage for regulation. For

most applications the minimum ESR ripple voltage is

dominated by PCB layout and the properties of SP or

POSCAP type output capacitors. For applications using

ceramic output capacitors the absolute minimum ESR

must be considered. Existing literature describing the ESR

requirements to prevent double pulsing does not

accurately predict the performance of constant on-time

controllers. A time domain model of the converter was

developed to generate equations for the minimum ESR

empirically. If the ESR is low enough the ripple voltage is

dominated by the charging of the output capacitor. This

ripple voltage lags the on-time due to the LC poles and

can cause double pulsing if the phase delay exceeds the

off-time of the converter. Refering to Figure 5, the

equation for the minimum ESR as a function of output

capacitance and switching frequency and duty cycle is;























−

•

•

•

π

•













•

+

•













+

>

D

1

2

Fs

Cout

2

Fs

200000

-

Fs

3

1

R3

R3

R2

ESR

Where D = Vout/Vin.