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TLE5012B 数据表(PDF) 44 Page - Infineon Technologies AG

部件名 TLE5012B
功能描述  Giant Magneto Resistance (GMR)-based principle
PDF  50 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

TLE5012B 数据表(HTML) 44 Page - Infineon Technologies AG

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TLE5012B
Specification
Data Sheet
44
Rev. 2.0, 2014-02
Figure 4-21 ADC test vectors
4.6
Supply Monitoring
The internal voltage nodes of the TLE5012B are monitored by a set of comparators in order to ensure error-free
operation. An over- or undervoltage condition must be active at least 256 periods of the digital clock to set the
corresponding error bits in the Status register. This works as digital spike suppression.
Over- or undervoltage errors trigger the S_VR bit of Status register. This error condition is signaled via the in the
Safety Word of the SSC protocol, the status nibble of the SPC interface or the lower diagnostic range of the PWM
interface.
110
-21700
111
-32768
1) Not allowed to use
Table 4-26 Test comparator threshold voltages
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Overvoltage detection
VOVG
2.80
V
1)
1) Not subject to production test - verified by design/characterization
VOVA
2.80
V
1)
VOVD
2.80
V
1)
VDD overvoltage
VDDOV
6.05
V
1)
VDD undervoltage
VDDUV
2.70
V
1)
GND - off voltage
VGNDoff
-0.55
V
1)
VDD - off voltage
VVDDoff
0.55
V
1)
Spike filter delay
tDEL
10
μs
1)
Table 4-25 ADC test vectors (cont’d)
Register bits
X/Y values (decimal)
Min.
Typ.
Max.
ADCTV_X
ADCTV_Y
0%
122.1%
100.0%
70%
141.4%



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