MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER

MP4433 Rev. 1.01

www.MonolithicPower.com

19

1/12/2018

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Internal Regulator and BIAS

Most of the internal circuitry is powered by the

5V internal regulator. This regulator takes VIN

and operates in the full VIN range. When VIN

exceeds 5V, the output of the regulator is in full

regulation. When VIN falls below 5V, the output

decreases following VIN. A decoupling ceramic

capacitor is needed close to VCC.

For better thermal performance, connect BIAS

to an external power supply between 5V to 18V.

The BIAS supply overrides VIN to power the

internal regulator. Using the BIAS supply allows

VCC to be derived from a high-efficiency

connect BIAS to ground if it is not being used.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The UVLO comparator monitors the output

voltage of the internal regulator (VCC). The

UVLO rising threshold is about 2.8V with a

150mV hysteresis.

Enable Control (EN)

EN is a digital control pin that turns the

regulator on and off. When EN is pulled below

its threshold voltage, the chip is put into the

lowest shutdown current mode. Pulling EN

above its threshold voltage turns on the part.

Do not float EN.

Power Good Indicator (PG)

The MP4433 has a power good (PG) indication.

PG is the open drain of a MOSFET and should

be connected to VCC or another voltage source

through

a

resistor

(e.g.:

100kΩ). In the

presence of an input voltage, the MOSFET

turns on so that PG is pulled low before SS is

ready. When the regulator output is within

±10% of its nominal output, the PG output is

pulled high after a delay (typically 30

μs). When

the output voltage moves outside this range

with a hysteresis, the PG output is pulled low

with a 50

μs delay to indicate a failure output

status.

Programmable Frequency

The oscillating frequency of the MP4433 can be

programmed either by an external frequency

resistor

or

by

a

logic

level

synchronization clock.

The frequency resistor

should be located

between FREQ and ground as close to the device

with Equation (1):

)

kHz

(

f

170000

)

kΩ

(

R

11

.

1

sw

FREQ



(1)

The calculated resistance may need fine tuning

with a bench test. Do not float FREQ even if an

external SYNC clock is added.

SYNC and PHASE

The internal oscillator frequency can also be

synchronized to an external clock ranging from

350kHz to 2.5MHz through SYNC. The external

clock should be at least 250kHz larger than the

amplitude of the SYNC clock is higher than

1.8V and the low amplitude is lower than 0.4V.

There is no pulse width requirement, but there

is always a parasitic capacitance of the pad, so

if the pulse width is too short, a clear rising and

falling edge may not be seen due to the

parasitic capacitance. A pulse longer than

100ns is recommended in application.

PHASE is used when two or more MP4433

devices are in parallel with the same SYNC

clock. Pulling PHASE high forces the device to

operate in-phase of the SYNC clock. Pulling

PHASE low forces the device to be 180°out-of-

phase of the SYNC clock. By setting different

voltages of PHASE, two devices can operate in

180° out-of-phase to reduce the total input

current ripple, so a smaller input bypass

capacitor can be used (see Figure 4). The

PHASE rising threshold is about 2.5V with a

400mV hysteresis.

SYNC

CLK

SW1

SW2

t

SW1: Phase high

SW2: Phase low

Figure 4: In-Phase and 180°Out-of-Phase