MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER

MP4433 Rev. 1.01

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24

1/12/2018

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can reduce the SW rising rate and voltage

spikes. This helps enhance EMI performance

and reduce voltage stress at a high VIN. A

higher resistance is better for

SW

spike

reduction but compromises efficiency. For a

tradeoff between EMI and efficiency, a ≤20Ω

PCB Layout Guidelines

(6)

Efficient PCB layout, especially of the input

capacitor

placement,

is

critical

for

stable

operation. For best results, refer to Figure 8 and

follow the guidelines below. A four-layer layout

is strongly recommended to achieve better

thermal performance.

1.

Place symmetric input capacitors as close

to VIN and GND as possible.

2.

Use a large ground plane to connect

directly to PGND. If the bottom layer is a

ground plane, add vias near PGND.

3.

Ensure that the high-current paths at GND

and VIN have short, direct, and wide traces.

4.

Place

the

ceramic

input

capacitor,

especially the small package size (0603)

input bypass capacitor, as close to VIN and

PGND

as

possible

to

minimize

high

frequency noise.

5.

Keep the connection of the input capacitor

and IN as short and wide as possible.

6.

Place the VCC capacitor as close to VCC

and GND as possible.

7.

Route SW and BST away from sensitive

analog areas, such as FB.

8.

Place the feedback resistors close to the

chip to ensure that the trace connecting to

FB is as short as possible.

9.

Use multiple vias to connect the power

planes to the internal layers.

NOTE:

6) The recommended PCB layout is based on Figure 9.

Top Layer

Inner Layer 1

Inner Layer 2

Bottom Layer

Figure 8: Recommended PCB Layout