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SAFC161RI 数据表(PDF) 21 Page - Siemens Semiconductor Group

部件名 SAFC161RI
功能描述  16-Bit CMOS Single-Chip Microcontroller
PDF  60 Pages
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制造商  SIEMENS [Siemens Semiconductor Group]
网页  http://www.siemens.com/
标志 SIEMENS - Siemens Semiconductor Group

SAFC161RI 数据表(HTML) 21 Page - Siemens Semiconductor Group

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Semiconductor Group
21
1998-05-01
C161RI
Figure 7
Block Diagram of GPT2
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 31
µs and 525 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval
after reset is 8.2 ms (@ 16 MHz).
GPT2 Timer T5
2n n=2...9
T5
Mode
Control
GPT2 Timer T6
T6
Mode
Control
GPT2 CAPREL
T6OTL
Interrupt
Request
CPU
Interrupt
Request
2n n=2...9
CPU
Clock
Clock
Interrupt
Request
CAPIN
Clear
Capture



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