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MP8758GL 数据表(PDF) 13 Page - Monolithic Power Systems |
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MP8758GL 数据表(HTML) 13 Page - Monolithic Power Systems |
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13 / 21 page ![]() MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER MP8758 Rev. 1.0 www.MonolithicPower.com 13 1/13/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. R1 R2 Ceramic SW FB Vo L R4 C4 IR4 IC4 IFB R9 Figure 7—Simplified Circuit in PWM Mode with External Ramp Compensation Figure 7 shows a simplified external ramp compensation (R4 and C4) for PWM mode. Chose R1, R2, R9 and C4 of the external ramp to meet the following condition: 12 9 SW 4 1 2 RR 11 R 2F C 5 R R ⎛⎞ × <× + ⎜⎟ π× × + ⎝⎠ (3) Where: R4 C4 FB C4 II I I =+ ≈ (4) And the Vramp on the VFB can then be estimated as: IN OUT 12 RAMP ON 44 1 2 9 VV R// R VT RC R // R R − =× × ×+ (5) The downward slope of the VFB ripple then follows − − == × OUT RAMP SLOPE1 off 4 4 V V V TR C (6) As can be seen from equation (6), if there is instability in PWM mode, we can reduce either R4 or C4. If C4 can not be reduced further due to limitation from equation (3), then we can only reduce R4. For a stable PWM operation, the Vslope1 should be design follow equation (7). SW ON -3 ESR OUT slope1 OUT OUT SW on TT +-R C Io 10 0.7 π 2 -V V + 2L C T -T × × ≥ ×× (7) Io is the load current. In skip mode, the downward slope of the VFB ripple is the same whether the external ramp is used or not. Figure 8 shows the simplified circuit of the skip mode when both the HS-FET and LS- FET are off. R1 R2 ESR Cout FB Vo Ro Figure 8—Simplified Circuit in skip Mode The downward slope of the VFB ripple in skip mode can be determined as follow: () REF SLOPE2 12 OUT V V (R R //Ro) C − = +× (8) Where Ro is the equivalent load resistor. As described in Figure 5, VSLOPE2 in the skip mode is lower than that is in the PWM mode, so it is reasonable that the jitter in the skip mode is larger. If one wants a system with less jitter during light load condition, the values of the VFB resistors should not be too big, however, that will decrease the light load efficiency. EN Control The regulator turns on when EN goes high. Conversely it turns off when EN goes low. For automatic start-up the EN pin can be pulled up to input voltage through a resistive voltage divider. Choose the values of the pull-up resistor (RUP from Vin pin to EN pin) and the pull-down resistor (RDOWN from EN pin to GND) to determine the automatic start-up voltage: UP DOWN IN START DOWN RR V1.25 (V) R − + =× (9) For example, for RUP=150kΩ and RDOWN=51kΩ, the − IN START V is set at 4.93V. To avoid noise, a 10nF ceramic capacitor from EN to GND is recommended. There is an internal Zener diode on the EN pin, which clamps the EN pin voltage to prevent it from running away. The maximum pull up current assuming a worst case 12V internal Zener clamp should be less than 1mA. |
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