MP8758–18V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER

MP8758 Rev. 1.0

www.MonolithicPower.com

14

1/13/2015

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Therefore, when EN is driven by an external logic

signal, the EN voltage should be lower than

12V.when EN is connected with VIN through a

pull-up resistor or a resistive voltage divider, the

resistance selection should ensure the maximum

pull up current less than 1mA.

If using a resistive voltage divider and VIN higher

than 12V, the allowed minimum pull-up resistor

IN

UP

DOWN

V(V) 12

12

1(mA)

R(k )

R

(k )

−

−<

ΩΩ

(10)

pull-down resistor is not connected), the

IN-START

V

is determined by input UVLO, and the minimum

resistor value is:

IN

UP

V(V) 12

R(k )

1(mA)

−

Ω>

(11)

A typical pull-up resistor is 499kΩ.

Soft Start

The MP8758 employs soft start (SS) mechanism

to ensure smooth output during power-up. When

the EN pin becomes high, the internal reference

voltage ramps up gradually; hence, the output

voltage ramps up smoothly, as well. Once the

reference voltage reaches the target value, the

soft start finishes and it enters into steady state

operation.

If the output is pre-biased to a certain voltage

during startup, the IC will disable the switching of

both high-side and low-side switches until the

voltage on the internal reference exceeds the

sensed output voltage at the FB node.

Power Good (PG)

The MP8758 has power-good (PGOOD) output

used to indicate whether the output voltage of the

regulator is ready or not. The PGOOD pin is the

open drain of a MOSFET. It should be connected

(e.g. 100k,). After the input voltage is applied, the

MOSFET is turned on so that the PGOOD pin is

pulled to GND before SS is ready. After FB

voltage reaches 95% of REF voltage, the

PGOOD pin is pulled high after a delay. The

PGOOD delay time is 0.45ms.

When the FB voltage drops to 85% of REF

voltage, the PGOOD pin will be pulled low.

Over Current Protection

MP8758 has cycle-by-cycle over current limiting

control. The current-limit circuit employs a

"valley" current-sensing algorithm. The part use

the Rds(on) of the low side MOSFET as a

current-sensing element. If the magnitude of the

current-sense signal is above the current-limit

threshold, the PWM is not allowed to initiate a

new cycle.

The trip level is fixed internally. The inductor

current is monitored by the voltage between GND

pin and SW pin. GND is used as the positive

current sensing node so that GND should be

connected to the source terminal of the bottom

MOSFET.

Since the comparison is done during the high

side MOSFET OFF and low side MOSFET ON

state, the OC trip level sets the valley level of the

inductor current. Thus, the load current at over-

current threshold, IOC, can be calculated as

follows:

Δ

OC

I

I

I _ limit

2

(12)

In an over-current condition, the current to the

load exceeds the current to the output capacitor;

thus the output voltage tends to fall off.

Eventually, it will end up with crossing the under

voltage protection threshold and shutdown. And

fault latching can be reset by EN going low or

Power-cycling of VIN.

Over/Under-Voltage Protection (OVP/UVP)

MP8758 monitors a resistor divided feedback

voltage to detect over and under voltage. When

the feedback voltage becomes higher than 115%

of the target voltage, the controller will enter

Dynamic Regulation Period. During this period,

the LS will off when the LS current goes to -1A,

this will then discharge the output and try to keep

it within the normal range. If the dynamic

regulation can not limit the increasing of the Vo,

once the feedback voltage becomes higher than

130% of the feedback voltage, the OVP

comparator output goes high and the circuit

latches as the high-side MOSFET driver off