MP8763D ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8763D Rev. 1.1

www.MonolithicPower.com

16

1/15/2015

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reasonable that the jitter in skip mode is larger

To achieve less jitter during ultra light load

condition, reduce R1 and R2, but that will

decrease the light load efficiency.

Configuring the EN Control

The regulator turns on when En goes high;

conversely it turns off when EN goes low. Do not

float the pin.

For automatic start-up, pull the EN pin up to input

voltage through a resistive voltage divider.

from the IN pin to the EN pin) and the pull-down

determine the automatic start-up voltage:

UP

DOWN

IN START

DOWN

(R

R

)

V1.5

(V)

R

−

+

=×

(11)

To reduce noise, add a 10nF ceramic capacitor

from EN to GND.

An internal zener diode on the EN pin clamps the

EN pin voltage to prevent run away. The

maximum pull up current assuming the worst

case 6V for the internal zener clamp should be

less than 1mA.

Therefore, when driving EN with an external logic

signal, use an EN voltage less than 6V. When

connecting EN to IN through a pull-up resistor or

a resistive voltage divider, select a resistance

that ensures a maximum pull-up current less than

1mA.

exceeds 6V, then the minimum resistance for the

IN

UP

DOWN

V6V

6V

1mA

RR

−

−≤

(12)

not connected), then the VCC UVLO threshold

value is:

IN

UP

V6V

R( )

1mA

−

≥Ω

(13)

A typical pull-up resistor is 100kΩ.

External VCC bias

An external 5V VCC bias can disable the internal

LDO, in this case, Vin can be as low as 2.5V.

Soft Start/Stop

The MP8763D employs a soft start/stop (SS)

mechanism to ensure a smooth output during

power-up and power shutdown. When the EN pin

goes high, an internal current source (20μA)

charges the SS capacitor. The SS capacitor

voltage takes over the REF voltage to the PWM

comparator. The output voltage smoothly ramps

up with the SS voltage. Once the SS voltage

reaches the REF voltage, it continues ramping up

comparator. At this point, soft start finishes and

the device enters steady state operation.

When the EN pin becomes low, the SS capacitor

voltage is discharged through a 10uA internal

current source. Once the SS voltage reaches

REF voltage, it takes over the control of the PWM

comparator. The output voltage will decrease

smoothly with SS voltage until zero level.

Determine the SS capacitor value as follows:

()

( )

( )

()

×μ

SS

SS

REF

Tms

I

A

CnF

VV

(14)

If the output capacitors are large, then avoid

setting a short SS time otherwise it would risk

hitting the current limit during SS.

Pre-Bias Startup

The MP8763D has been designed for monotonic

startup into pre-biased loads. If the output is pre-

biased to a certain voltage during startup, the IC

will disable switching for both high-side and low-

side switches until the voltage on the soft-start

capacitor exceeds the sensed output voltage at

the FB pin.

Power Good (PG)

The MP8763D has a power-good (PG) output.

The PG pin is the open drain of a MOSFET.

Connect

it

to

VCC

or

some

other