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MP8763DGL 数据表(PDF) 20 Page - Monolithic Power Systems |
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MP8763DGL 数据表(HTML) 20 Page - Monolithic Power Systems |
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20 / 25 page ![]() MP8763D ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER MP8763D Rev. 1.1 www.MonolithicPower.com 20 1/15/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 2 R V 2 1 V V 2 1 V V 1 R RAMP REF RAMP REF OUT × × + × − − = (19) For best results, select a CDC Value at least 10× C4 for better DC blocking performance, but smaller than 0.47µF account for start-up performance. To use a larger CDC for better FB noise immunity, reduce R1 and R2 to limit effects on system start-up. Note that even with Cdc, the load and line regulation are still related to VRAMP. R1 R2 Ceramic SW FB VOUT L CDC R4 C4 Figure12—Simplified Ceramic Capacitor Circuit with DC Blocking Capacitor Input Capacitor The input current to the step-down converter is discontinuous, and therefore, requires a capacitor to supply the AC current to the step- down converter while maintaining the DC input voltage. Use ceramic capacitors for best performance. During layout, Place the input capacitors as close to the IN pin as possible. The capacitance can vary significantly with temperature. Use capacitors with X5R and X7R ceramic dielectrics because they are fairly stable over a wide temperature range. The capacitors must also have a ripple current rating that exceeds the converter’s maximum input ripple current. Estimate the input ripple current as follows: ) V V 1 ( V V I I IN OUT IN OUT OUT CIN − × × = (20) The worst-case condition occurs at VIN = 2VOUT, where: 2 I I OUT CIN = (21) For simplification, choose an input capacitor with an RMS current rating that exceeds half the maximum load current. The input capacitance value determines the converter input voltage ripple. Select a capacitor value that meets any input voltage ripple requirements. Estimate the input voltage ripple as follows: ) V V 1 ( V V C F I V IN OUT IN OUT IN SW OUT IN − × × × = Δ (22) The worst-case condition occurs at VIN = 2VOUT, where: IN SW OUT IN C F I 4 1 V × × = Δ (23) Output Capacitor The output capacitor maintains the DC output voltage. Use ceramic capacitors or POSCAPs. Estimate the output voltage ripple as: ) C F 8 1 R ( ) V V 1 ( L F V V OUT SW ESR IN OUT SW OUT OUT × × + × − × × = Δ (24) When using ceramic capacitors, the capacitance dominates the impedance at the switching frequency. The capacitance also dominates the output voltage ripple. For simplification, estimate the output voltage ripple as: ) V V 1 ( C L F 8 V V IN OUT OUT 2 SW OUT OUT − × × × × = Δ (25) The ESR only contributes minimally to the output voltage ripple, thus requiring an external ramp to stabilize the system. Design the external ramp with R4 and C4 as per equation 5, 8 and 9. |
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