Data Sheet

ADL5320

SOLDERING INFORMATION AND RECOMMENDED

PCB LAND PATTERN

Figure 35 shows the recommended land pattern for the ADL5320.

To minimize thermal impedance, the exposed paddle on the

SOT-89 package underside is soldered down to a ground plane

along with Pin 2. If multiple ground layers exist, stitch them

together using vias. For more information on land pattern design

and layout, refer to the Application Note AN-772, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP).

The land pattern on the ADL5320 evaluation board provides a

temperature at the top of the SOT-89 package is found with an

IR temperature gun. Thermal simulation suggests a junction

temperature 10°C higher than the top of the package temperature.

With additional ambient temperature and input/output power

1.50mm

3.00mm

1.80mm

0.86mm

0.762mm

0.635mm

0.86mm

0.20mm

Figure 35. Recommended Land Pattern

Rev. B | Page 13 of 20