MP3313 Rev1.0

www.MonolithicPower.com

19

8/2/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2017 MPS. All Rights Reserved.

Table 3: Register Mapping

Add

D7

D6

D5

D4

D3

D2

D1

D0

00H

DEV_ID3

DEV_ID2

DEV_ID1

DEV_ID0

REV_ID3

REV_ID2

REV_ID1

REV_ID0

01H

RESERVED

SRST

10H

RESERVED

CH3EN

CH2EN

CH1EN

EN

11H

MAPMD

BRTMD2:0

SLPEN

TSLP2:0

12H

PWMSR1:0

PWM_P

HYS2:0

FILTER1:0

13H

NA

FS_SHFT

FS

L_MIN

OVP1:0

CL1:0

14H

FL_CL

IFL6:0

15H

FS_AUTOH7:0

16H

FS_AUTOL7:0

17H

FL_T3:0

RESERVED

FL_EN

18H

RESERVED

BRT2:0

19H

BRT10:3

1EH

S_TH1:0

SLP_MD1:0

OVP_MD1:0

OTP_SD

OCP_SD

1FH

RESERVED

FT_UVP

FT_OLP

FT_SLP

FT_OTP

FT_OCP

FT_OVP

Table 4: Chip ID Register

Addr: 0x00

Bit

Bit Name

Access

Default

Description

7:4

DEV_ID

r

000

Device ID.

3:0

REV_ID

r

0001

Revision ID.

Table 5: Software Reset Register

Addr: 0x01

Bit

Bit Name

Access

Default

Description

7:1

N/A

r

N/A

Reserved.

0

SRST

r/w

0

Software reset bit.

0: normal operation

1: device resets, all registers are reset to default (this bit automatically

resets back to 0)

Table 6: Enable Register

Addr: 0x10

Bit

Bit Name

Access

Default

Description

7:4

N/A

r

N/A

Reserved.

3

CH3EN

r/w

1

LED3 enable bit.

1: LED3 enabled

0: LED3 disabled

2

CH2EN

r/w

1

LED2 enable bit.

1: LED2 enabled

0: LED2 disabled

1

CH1EN

r/w

1

LED1 enable bit.

1: LED1 enabled

0: LED1 disabled

0

EN

r/w

1

IC enable bit

1: IC enabled

0: IC disabled